Contact geometry having a gate silicon length decoupled from a transistor length

Abstract

A semiconductor device structure includes an active region positioned in a semiconductor substrate and a gate structure of a transistor positioned above the active region. The gate structure includes a gate insulating layer, a gate metal layer positioned above the gate insulating layer and a trimmed gate electrode material layer positioned above the gate metal layer. A length of at least a portion of the trimmed gate electrode material layer in a gate length direction of the transistor is less than a length of at least the gate metal layer in the gate length direction.

What is claimed: 
     
         1 . A semiconductor device structure, comprising:
 an active region positioned in a semiconductor substrate; and   a gate structure of a transistor positioned above said active region, said gate structure comprising:
 a gate insulating layer; 
 a gate metal layer positioned above said gate insulating layer; and 
 a trimmed gate electrode material layer positioned above said gate metal layer, wherein a length of at least a portion of said trimmed gate electrode material layer in a gate length direction of said transistor is less than a length of at least said gate metal layer in said gate length direction. 
   
     
     
         2 . The semiconductor device structure of  claim 1 , wherein said trimmed gate electrode material layer has a rounded tip portion. 
     
     
         3 . The semiconductor device structure of  claim 1 , wherein said length of said at least said portion of said trimmed gate electrode material layer in said gate length direction of said transistor is less than a length of said gate insulating layer in said gate length direction. 
     
     
         4 . The semiconductor device structure of  claim 1 , further comprising a sidewall spacer positioned adjacent to sidewalls of said gate structure, wherein said sidewall spacer covers at least an upper surface portion and a sidewall surface portion of said gate metal layer. 
     
     
         5 . The semiconductor device structure of  claim 4 , wherein said sidewall spacer further covers at least a sidewall surface portion of said gate insulating layer. 
     
     
         6 . The semiconductor device structure of  claim 4 , wherein said sidewall spacer is a sidewall spacer structure comprising a first spacer and a liner spacer layer positioned between said first spacer and said gate structure. 
     
     
         7 . The semiconductor device structure of  claim 6 , wherein said liner spacer layer contacts said at least said upper surface portion of said gate metal layer. 
     
     
         8 . The semiconductor device structure of  claim 6 , wherein said liner spacer layer has a “W” shape when viewed in a cross-section taken in said gate length direction. 
     
     
         9 . The semiconductor device structure of  claim 1 , wherein said gate insulating layer comprises a high-k dielectric material and said gate metal layer comprises one of titanium, tantalum and ruthenium. 
     
     
         10 . The semiconductor device structure of  claim 1 , wherein said gate electrode material layer comprises one of amorphous silicon, polysilicon and silicon/germanium. 
     
     
         11 . The semiconductor device structure of  claim 1 , further comprising source and drain regions positioned in said active region and laterally adjacent to sidewalls of said gate structure. 
     
     
         12 . The semiconductor device structure of  claim 11 , further comprising a silicide contact region positioned in said source and drain regions. 
     
     
         13 . A semiconductor device structure, comprising:
 an active region positioned in a semiconductor substrate;   a gate structure of a transistor positioned above said active region, said gate structure comprising:
 a gate insulating layer; 
 a gate metal layer positioned above said gate insulating layer; and 
 a gate electrode material layer positioned above said gate metal layer, wherein sidewall surfaces of said gate electrode material layer are laterally offset from respective sidewall surfaces of at least one of said gate metal layer and said gate insulating layer such that said gate electrode material layer covers a first upper surface portion of said at least one of said gate metal layer and said gate insulating layer but does not cover a second upper surface portion of said at least one of said gate metal layer and said gate insulating layer; and 
   a sidewall spacer positioned adjacent to sidewalls of said gate structure, said sidewall spacer covering at least said second upper surface portion and said respective sidewall surfaces of said at least one of said gate metal layer and said gate insulating layer.   
     
     
         14 . The semiconductor device structure of  claim 13 , wherein said sidewall surfaces of said gate electrode material layer are laterally offset from said respective sidewall surfaces of said gate metal layer such that said gate electrode material layer covers a first upper surface portion of said gate metal layer but does not cover a second upper surface portion of said gate metal layer. 
     
     
         15 . The semiconductor device structure of  claim 14 , wherein a length of at least a portion of said gate electrode material layer in a gate length direction of said transistor is less than a length of each of said gate metal layer and said gate insulating layer in said gate length direction. 
     
     
         16 . The semiconductor device structure of  claim 14 , wherein said sidewall spacer covers said second upper surface portion of said gate metal layer and said respective sidewall surfaces of each of said gate metal layer and said gate insulating layer. 
     
     
         17 . The semiconductor device structure of  claim 13 , wherein said sidewall spacer is a sidewall spacer structure comprising a first spacer and a liner spacer layer positioned between said first spacer and said gate structure, said liner spacer layer contacting said second upper surface portion of said at least one of said gate metal layer and said high-k gate insulating layer. 
     
     
         18 . The semiconductor device structure of  claim 13 , wherein said gate insulating layer comprises a high-k dielectric material and said gate metal layer comprises one of titanium, tantalum and ruthenium. 
     
     
         19 . The semiconductor device structure of  claim 13 , wherein said gate electrode material layer comprises one of amorphous silicon, polysilicon and silicon/germanium. 
     
     
         20 . A semiconductor device structure, comprising:
 an active region positioned in a semiconductor substrate;   a gate structure of a transistor positioned above said active region, said gate structure comprising:
 a gate insulating layer comprising a high-k dielectric material; 
 a gate metal layer positioned above said gate insulating layer; and 
 a gate electrode material layer positioned above said gate metal layer, said gate electrode material layer comprising one of amorphous silicon, polysilicon and silicon/germanium, wherein a length of at least a portion of said gate electrode material layer in a gate length direction of said transistor is less than a length of each of said gate metal layer and said gate insulating layer in said gate length direction, and wherein said gate electrode material layer covers a first upper surface portion of said gate metal layer but does not cover a second upper surface portion of said gate metal layer; and 
   a sidewall spacer positioned adjacent to sidewalls of said gate structure, said sidewall spacer covering said second upper surface portion of said gate metal layer and sidewall surfaces of each of said gate metal layer and said gate insulating layer.