Semiconductor package and method of manufacturing thereof

Abstract

A semiconductor package comprises a semiconductor chip having an active surface with a conductive pad thereon; an electroplated Au—Sn alloy bump over the active surface; and a (glass) substrate comprising conductive traces electrically coupling with the electroplated Au—Sn alloy bump, wherein the electroplated Au—Sn alloy bump has a composition from about Au 0.85 Sn 0.15 to about Au 0.75 Sn 0.25 in weight percent uniformly distributed from an end in proximity to the active surface to an end in proximity to the substrate. A method of manufacturing a semiconductor package comprises forming patterns of conductive pads on an active surface of a semiconductor chip; electroplating Au—Sn alloy bump over the conductive pads; and bonding the semiconductor chip on a corresponding conductive trace on a substrate by a reflow operation or a thermal press operation.

What is claimed is: 
     
         1 . A semiconductor package, comprising:
 a semiconductor chip having an active surface with a conductive pad thereon;   an electroplated Au—Sn alloy bump over the active surface; and   a substrate comprising conductive traces electrically coupling with the electroplated Au—Sn alloy bump,   wherein the electroplated Au—Sn alloy bump has a composition from about Au 0.85 Sn 0.15  to about Au 0.75 Sn 0.25  in weight percent uniformly distributed from an end in proximity to the active surface to an end in proximity to the substrate.   
     
     
         2 . The semiconductor package of  claim 1 , further comprising a conductive pillar between the electroplated Au—Sn alloy bump and the conductive pad. 
     
     
         3 . The semiconductor package of  claim 1 , wherein a height of the electroplated Au—Sn alloy bump is in a range of from about 7 μm to about 31 μm. 
     
     
         4 . The semiconductor package of  claim 1 , wherein an intermetallic compound is between the conductive pillar and the electroplated Au—Sn alloy bump. 
     
     
         5 . The semiconductor package of  claim 1 , wherein the conductive pad is an electrode and the electroplated Au—Sn alloy bump is between the electrode and the conductive traces. 
     
     
         6 . The semiconductor package of  claim 1 , wherein the semiconductor chip is a light-emitting diode (LED). 
     
     
         7 . The semiconductor package of  claim 6 , wherein the conductive pad is a p-type electrode and another conductive pad is an n-type electrode, and the electroplated Au—Sn alloy bump is between the p-type electrode and the conductive traces and another electroplated Au—Sn bump is between the n-type electrode and the conductive traces. 
     
     
         8 . The semiconductor package of  claim 7 , wherein a height of the two electroplated Au—Sn alloy bumps is in a range of from about 3 μm to about 10 μm, a width of the two electroplated Au—Sn alloy bumps is in a range of from 200-600 μm, and a length of the two electroplated Au—Sn alloy bumps is in a range of from 500-1500 μm. 
     
     
         9 . The semiconductor package of  claim 1 , wherein the semiconductor package is a chip-on-film (COF) package. 
     
     
         10 . The semiconductor package of  claim 1 , wherein the semiconductor package is a chip-on-glass (COG) package. 
     
     
         11 . A semiconductor package, comprising:
 a semiconductor chip having an active surface with a conductive pad thereon;   an electroplated Au—Sn alloy bump over the active surface; and   a glass substrate comprising conductive traces electrically coupling with the electroplated Au—Sn alloy bump,   wherein the electroplated Au—Sn alloy bump has a composition from about Au 0.85 Sn 0.15  to about Au 0.75 Sn 0.25  in weight percent uniformly distributed from an end in proximity to the active surface to an end in proximity to the glass substrate.   
     
     
         12 . The semiconductor package of  claim 11 , further comprising a conductive pillar between the electroplated Au—Sn alloy bump and the conductive pad. 
     
     
         13 . The semiconductor package of  claim 11 , wherein no anisotropic conductive film (ACF) is positioned between the semiconductor chip and the glass substrate. 
     
     
         14 . The semiconductor package of  claim 11 , wherein an intermetallic compound is between the conductive pillar and the electroplated Au—Sn alloy bump. 
     
     
         15 . The semiconductor package of  claim 11 , wherein each of the conductive pillars is made of a material selected from a group consisting of Au, Cu, Ag, and alloys thereof. 
     
     
         16 . A method of manufacturing a semiconductor package, comprising:
 forming patterns of conductive pads on an active surface of a semiconductor chip;   electroplating Au—Sn alloy bump over the conductive pads; and   bonding the semiconductor chip on a corresponding conductive trace on a substrate by a reflow operation or a thermal press operation.   
     
     
         17 . The method of  claim 16 , wherein the electroplating Au—Sn alloy bump as recited in  claim 1  comprises:
 immersing the semiconductor chip in a Au—Sn electroplating bath; 
 controlling current density flowing through the Au—Sn electroplating bath within a range of form about 0.2 ASD to about 1.0 ASD; and 
 maintaining a temperature of the Au—Sn electroplating bath within a range of from about 35 degrees Celsius to about 60 degrees Celsius. 
 
     
     
         18 . The method of  claim 16 , wherein a rate of electroplating Au—Sn alloy bump is controlled in a range of from about 0.2 μm/min to about 0.4 μm/min. 
     
     
         19 . The method of  claim 16 , wherein bonding the semiconductor chip on the corresponding conductive trace comprises heating the semiconductor chip to achieve a temperature at an interface between the Au—Sn alloy bump and the conductive trace of from about 280 degrees Celsius to about 320 degrees Celsius. 
     
     
         20 . The method of  claim 16 , wherein no annealing operation is conducted after the electroplating operation and before the bonding operation.