Method of efficiently implementing a mpeg-4 avc deblocking filter on an array of parallel processors

Abstract

A method for implementing a deblocking filter including the steps of (A) reading pixel values for a plurality of macroblocks of an unfiltered video frame from an input buffer into a working buffer, where the working buffer has dimensions determined by a predefined input region of the deblocking filter and a portion of the working buffer forms a filter output region of the deblocking filter, (B) sequentially processing the pixel values in the working buffer through a plurality of filter processing stages using an array of software-configurable general purpose parallel processors, where each of the plurality of filter processing stages operates on a respective set of the pixel values in the working buffer, and (C) writing filtered pixel values from the filter output region of the working buffer to an output buffer after the plurality of filter processing stages are completed.

1 . A method comprising:
 processing pixel values in a working buffer in parallel using an array of parallel processors by processing the pixel values in the working buffer through a plurality of filter processing stages including:   a first filter processing stage configured to filter pixel values across vertical edges in pixel values in the working buffer; and   a second filter processing stage configured to filter pixel values across horizontal edges in pixel values in the working buffer;   determining the plurality of filter processing stages have been processed; and   writing the filtered pixel values from the working buffer to an output buffer.   
     
     
         2 . The method of  claim 1 , wherein each of the plurality of filter processing stages computes filtered pixel values by applying a predefined filter on the pixel values in the working buffer. 
     
     
         3 . The method of  claim 1 , wherein for the first filter processing stage, the array of parallel processors processes rows of the pixel values within the pixel values in the working buffer concurrently. 
     
     
         4 . The method of  claim 1 , wherein for the second filter processing stage, the array of parallel processors processes columns of the pixel values within the pixel values in the working buffer concurrently. 
     
     
         5 . The method of  claim 1 , wherein each of the filter processing stages writes the filtered pixels back to a respective stage output region of the working buffer. 
     
     
         6 . The method of  claim 1 , wherein each of the filter processing stages processes a different filter region of a plurality of filter regions of the working buffer. 
     
     
         7 . The method of  claim 1 , wherein the wherein the plurality of filter processing stages form a MPEG-4 part 10 compliant deblocking filter and the filtered pixel values are computed using an adaptive multi-tap filter applied at right angles to edges being filtered. 
     
     
         8 . An apparatus comprising:
 a working buffer configured to store pixel values during filter processing;   an output buffer configured to store filtered pixel values; and   an array of parallel processors, the array of parallel processors being configured to process the pixel values in the working buffer through a plurality of filter processing stages including:   a first filter processing stage configured to filter pixel values across vertical edges in pixel values in the working buffer; and   a second filter processing stage configured to filter pixel values across horizontal edges in pixel values in the working buffer.   
     
     
         9 . The apparatus of  claim 8 , wherein the array of parallel processors are configured to compute filtered pixel values for each of the plurality of filter processing stages by applying a predefined filter on the pixel values in the working buffer. 
     
     
         10 . The apparatus of  claim 8 , wherein for the first filter processing stage, the array of parallel processors processes rows of pixel values within the pixel values in the working buffer concurrently. 
     
     
         11 . The apparatus of  claim 8 , wherein for the second filter processing stage, the array of parallel processors processes columns of pixel values within the pixel values in the working buffer concurrently. 
     
     
         12 . The apparatus of  claim 8 , wherein the array of parallel processors are configured to write the filtered pixels back to a respective stage output region of the working buffer for each of the plurality of filter processing stages. 
     
     
         13 . The apparatus of  claim 8 , wherein the array of parallel processors are configured to process a different filter region of a plurality of filter regions of the working buffer for each of the plurality of filter processing stages. 
     
     
         14 . The apparatus of to  claim 8 , wherein the plurality of filter processing stages form a MPEG-4 part 10 compliant deblocking filter and the filtered pixel values are computed using an adaptive multi-tap filter applied at right angles to edges being filtered. 
     
     
         15 . A computing system comprising:
 at least one processor; and   a memory device including instructions that, when executed by the at least one processor, cause the computing system to:   process pixel values in a working buffer in parallel using an array of parallel processors by processing the pixel values in the working buffer through a plurality of filter processing stages including:   a first filter processing stage configured to filter pixel values across vertical edges in pixel values in the working buffer; and   a second filter processing stage configured to filter pixel values across horizontal edges in pixel values in the working buffer;   determine the plurality of filter processing stages have been processed; and   write the filtered pixel values from the working buffer to an output buffer.   
     
     
         16 . The computing system of  claim 15 , wherein each of the plurality of filter processing stages computes filtered pixel values by applying a predefined filter on the pixel values in the working buffer. 
     
     
         17 . The computing system of  claim 15 , wherein for the first filter processing stage, the array of parallel processors processes rows of the pixel values within the pixel values in the working buffer concurrently. 
     
     
         18 . The computing system of  claim 15 , wherein for the second filter processing stage, the array of parallel processors processes columns of the pixel values within the pixel values in the working buffer concurrently. 
     
     
         19 . The computing system of  claim 15 , wherein each of the filter processing stages writes the filtered pixels back to a respective stage output region of the working buffer. 
     
     
         20 . The computing system of  claim 15 , wherein the plurality of filter processing stages form a MPEG-4 part 10 compliant deblocking filter and the filtered pixel values are computed using an adaptive multi-tap filter applied at right angles to edges being filtered.