Decoder, receiver, and electronic device

Abstract

Power consumption of a decoder is reduced. The decoder includes an FPGA. The FPGA performs at least one processing to decode the data. In the case where the data has first resolution, an input data signal of the FPGA is a binary signal and a clock frequency of the FPGA is a first frequency. In the case where the resolution of the data is lower than the first resolution, the input data signal of the FPGA is a pulse signal and the FPGA operates at a second frequency which is lower than the first frequency. The FPGA operates at the first clock frequency in the case of decoding 8K data and the FPGA operates at the second clock frequency in the case of decoding 4K or 2K data.

1 . A decoder having a function of decoding data, comprising:
 an FPGA is configured to perform at least one processing to decode the data,   wherein the FPGA is configured to process a binary signal as an input data signal when the data has a first resolution, and   wherein the FPGA is configured to process a pulse signal as the input data signal when the resolution of the data is lower than the first resolution.   
     
     
         2 . The decoder according to  claim 1 ,
 wherein the FPGA comprises a logic element, the logic element comprising:
 a data input portion configured to be input with the input data signal; 
 an arithmetic circuit configured to perform an arithmetic operation on the input data signal; and 
 a data output portion configured to process a data signal obtained as a result of the arithmetic operation performed in the arithmetic circuit and generates an output data signal, 
   wherein, the data input portion is configured so that the input data signal can be converted into a binary signal, the data output portion is configured so that the output data signal can be converted into a pulse signal, and power gating of the arithmetic circuit can be performed when the resolution of the data is lower than the first resolution.   
     
     
         3 . A decoder having a function of decoding data, comprising:
 a circuit configured to perform a first processing to decode the data,   wherein the circuit is configured to process a binary signal as an input data signal when the data has a first resolution, and   wherein the circuit is configured to process a pulse signal as the input data signal when the data has a resolution lower than the first resolution.   
     
     
         4 . The decoder according to  claim 3 ,
 the circuit comprising:
 a data input portion to which the input data signal is input; 
 a dedicated circuit that performs the first processing; and 
 a data output portion that generates an output data signal from a signal processed in the dedicated circuit, 
   wherein the data input portion is configured so that the input data signal can be converted into a binary signal, the data output portion is configured so that the output data signal can be converted into a pulse signal, and power gating of the dedicated circuit can be performed when the resolution of the data is lower than the first resolution.   
     
     
         5 . The decoder according to  claim 1 ,
 wherein the FPGA comprises a configuration memory,   wherein the configuration memory comprises a storage capacitor and a transistor connected to the storage capacitor, and   wherein a channel formation region of the transistor is formed from an oxide semiconductor.   
     
     
         6 . The decoder according to  claim 3 ,
 wherein the FPGA comprises a configuration memory,   wherein the configuration memory comprises a storage capacitor and a transistor connected to the storage capacitor, and   wherein a channel formation region of the transistor is formed from an oxide semiconductor.   
     
     
         7 . The decoder according to  claim 3 , further comprising:
 a data input portion configured to be input with the input data signal; and   a data output portion configured to generate an output data signal from a signal processed in the dedicated circuit,   wherein a configuration memory is connected to the data input portion and the data output portion,   wherein the configuration memory comprises a storage capacitor and a transistor connected to the storage capacitor, and   wherein a channel formation region of the transistor is formed from an oxide semiconductor.   
     
     
         8 . A receiver having a function of receiving a broadcast signal, comprising:
 a demodulator; and   the decoder according to  claim 1 ,   wherein the demodulator has a function of demodulating the broadcast signal, and   wherein the decoder has a function of processing the demodulated broadcast signal.   
     
     
         9 . A receiver having a function of receiving a broadcast signal, comprising:
 a demodulator; and   the decoder according to  claim 3 ,   wherein the demodulator has a function of demodulating the broadcast signal, and   wherein the decoder has a function of processing the demodulated broadcast signal.   
     
     
         10 . An electronic device comprising:
 a display portion; and   the receiver according to  claim 8 .   
     
     
         11 . An electronic device comprising:
 a display portion; and   the receiver according to  claim 9 .