Encoders, decoders, codecs and systems and processes for their operation and manufacture

Abstract

A block encode circuit ( 800 ) including a scanner ( 820 ) operable to scan a block having data values spaced apart in the block by run-lengths to produce a succession of pairs of values of Level and Run representing each data value and run-length, and wherein the Level values include one or more AC values succeeded by a DC value in the succession, and a Run-Level encoder ( 830 ) responsive to said scanner ( 820 ) to encode the values of Level and Run in a same AC to DC order as in the succession of pairs of values from said scanner ( 820 ) to deliver an encoded output. Other encoders, decoders, codecs and systems and processes for their operation and manufacture are disclosed.

What is claimed is: 
     
         1 . A decode circuit comprising:
 a Run-Level decoder operable to deliver a succession of pairs of values, each pair including a Run value and a Level value; and   an inverse scanner responsive to the succession of pairs of values to populate a block with the Level values including one or more AC values and a DC value, the Level values spaced apart in the block by runs having lengths represented by the Run values, and the inverse-scanner is operable to sequentially populate the block using the Level values and the Run values in a same AC to DC order as in the succession of pairs of values from the Run-Level decoder.   
     
     
         2 . The decode circuit of  claim 1  in which the Run-Level decoder includes a memory space for only a single coding table and including a symbol decoder to supply the succession of pairs of values, the symbol decoder coupled to directly access only the memory space for the coding table information to reduce coding table memory space. 
     
     
         3 . The decode circuit of  claim 1  including a store for a plurality of different coding tables, and a selection circuit operable to supply a selection signal to the store to deliver a single applicable coding table at a time to the memory space. 
     
     
         4 . The decode circuit of claim  23  in which the store is a re-usable store selected from the group consisting of 1) cache, and 2) random access memory (RAM), whereby the memory space for the single coding table saves overall space for the decode circuit. 
     
     
         5 . The decode circuit of  claim 1  including a selection circuit responsive to the Run-Level decoder to select information to feed into the Run-Level decoder. 
     
     
         6 . An electronic system comprising:
 a modem operable to receive a transmission;   a Run-Level decoder responsive to the transmission to deliver a succession of pairs of values, each pair including a Run value and a Level value;   an inverse scanner responsive to the succession of pairs of values to populate a block with the Level values including one or more AC values and a DC value, the Level values spaced apart in the block by runs having lengths represented by the Run values, and the inverse-scanner operable to sequentially populate the block using the Level values and the Run values in a same order as in the succession of pairs of values from the Run-Level decoder; and   a display circuit operable in response to the inverse scanner to form an image signal.   
     
     
         7 . The electronic system of  claim 6  adapted to form a device selected from the group consisting of 1) cellular telephone, 2) projector, 3) mobile entertainment device, 4) personal computer.