Autoconfigurable Phase-Locked Loop Which Automatically Maintains a Constant Damping Factor and Adjusts the Loop Bandwidth to a Constant Ratio of the Reference Frequency

Abstract

A phase-locked loop (PLL) includes a state machine programmed to automatically produce a set of control signals to select a charge-pump current and integrating capacitance value to automatically adjust a loop bandwidth of the PLL. A charge-pump DAC generates a charge-pump current of magnitude controlled by the state machine control signals. An integrator integrates the charge-pump output current to produce an integrated charge-pump output signal. The integrator has a plurality of capacitors switchably selected by control signals from the state machine to produce an integrating capacitance value. A voltage controlled oscillator (VCO) produces a PLL output frequency in response to the integrated charge-pump output signal.

1 . A phase-locked loop (PLL), comprising:
 a frequency detector circuit for estimating a frequency of a reference frequency signal by counting a number of cycles of the reference frequency signal over a fixed period of time;   a phase detector for generating up and down command signals in response to phase differences between the reference frequency signal and a frequency signal related to a base PLL output frequency signal;   a circuit for producing control signals in dependence upon the frequency detected by said frequency detector;   a charge-pump DAC for generating a charge-pump current, said charge-pump DAC being connected to receive said up and down command signals and control signals from said circuit for producing control signals to produce a charge-pump output current of magnitude selected by said control signals from said circuit for producing control signals;   an integrator for integrating said charge-pump output current, said integrator including having plurality of capacitors switchably selected by control signals from said circuit for producing control signals to produce an integrating capacitance value; and   a voltage controlled oscillator (VCO) for producing the base PLL output frequency signal in response to said integrated charge-pump output signal.   
     
     
         2 . The PLL of  claim 1  wherein said circuit for producing control signals is a state machine. 
     
     
         3 . The PLL of  claim 2  wherein said state machine is programmed to automatically produce a set of control signals to select a charge-pump current and integrating capacitance value to automatically adjust a loop bandwidth of said PLL. 
     
     
         4 . The PLL of  claim 2  wherein said state machine is programmed to automatically produce a set of control signals to select a charge-pump current and integrating capacitance value to automatically adjust a loop bandwidth of said PLL over an entire range of reference frequencies over which said PLL operates. 
     
     
         5 . The PLL of  claim 2  wherein said integrator comprises a resistor and a first capacitor DAC circuit between said charge-pump output and a reference potential and a second capacitor DAC circuit between said charge-pump output and the reference potential. 
     
     
         6 . The PLL of  claim 5  wherein each of said capacitor DAC circuit comprises a plurality of capacitors and a corresponding plurality of switches, each switch controlled by a command signal from said state machine to interconnect selected capacitances to produce a desired integrating capacitance value. 
     
     
         7 . The PLL of  claim 2  wherein said charge-pump DAC comprises a first set of current sources that are selected in response to an up command from said phase detector and a second set of current sources that are selected in response to a down command from said phase detector. 
     
     
         8 . The PLL of  claim 1  further comprising a transconductance amplifier for receiving said integrated charge-pump output signal to provide a frequency controlling signal to said VCO. 
     
     
         9 . The PLL of  claim 2  further comprising a frequency divider to divide the PLL base output frequency signal to produce the frequency signal related to the base PLL output frequency. 
     
     
         10 . The PLL of  claim 2  further comprising a reference frequency divider to produce an internal reference frequency to establish states of said state machine.