Temperature compensated pll calibration

Abstract

In some embodiments, provided are AFC circuits and methods for calibrating a second setting of an oscillator while a first setting is controlled by a temperature compensated control.

1 . (canceled) 
     
     
         2 . An apparatus comprising:
 a phase frequency detector (PFD);   a charge pump coupled to the PFD;   a low pass filter (LPF) coupled to the charge pump;   an oscillator;   a first switch operable to couple an input of the oscillator with the LPF during a first operation mode;   a circuit to provide an output which is a temperature compensated calibrated voltage; and   a second switch operable to couple the input of the oscillator with the output of the circuit during a second operation mode.   
     
     
         3 . The apparatus of  claim 2 , wherein the first operation mode is a normal mode, wherein the second operation mode is a calibration mode, and wherein the second operation mode is to be performed before the first operation mode. 
     
     
         4 . The apparatus of  claim 2 , wherein the circuit comprises:
 a temperature sensor; and   a digital-to-analog converter coupled to the temperature sensor, wherein the DAC is to provide the output of the circuit.   
     
     
         5 . The apparatus of  claim 4 , wherein the digital to analog converter is generate one or more signals indicating a high limit and a low limit for the temperature calibrated voltage. 
     
     
         6 . The apparatus of  claim 5  comprises:
 a first comparator to compare an operational control voltage with the high limit; and 
 a second comparator to compare the operational control voltage with the low limit. 
 
     
     
         7 . The apparatus of  claim 6 , wherein a number of enabled capacitors in the oscillator are reduced if an output of the first comparator indicates that the operational control voltage is higher than the high limit. 
     
     
         8 . The apparatus of  claim 6 , wherein a number of enabled capacitors in the oscillator are increased if an output of the second comparator indicates that the operational control voltage is lower than the low limit. 
     
     
         9 . The apparatus of  claim 2  comprises a calibration logic to provide a code to the oscillator, wherein the calibration logic is coupled to the oscillator. 
     
     
         10 . The apparatus of  claim 9  comprises a frequency detector coupled to the calibration logic, wherein the frequency detector is to compare a frequency of the oscillator with a reference clock. 
     
     
         11 . The apparatus of  claim 2 , wherein the oscillator is part of an on-chip transmitter clock generator. 
     
     
         12 . The apparatus of  claim 2 , wherein the oscillator is an Inductor Capacitor Voltage Controlled Oscillator (LCVCO). 
     
     
         13 . An apparatus comprising:
 a digitally controlled oscillator (LDO);   a first control to adjust capacitor settings of the DCO by a coarse amount;   a second control to adjust the capacitor settings of the DCO by a fine amount; and   an automatic frequency control (AFC) logic which is to provide the first and second controls such that the second control is to have an associated code which is near a middle of a range of the associated code when a temperature is to be at a mid-range value.   
     
     
         14 . The apparatus of  claim 13 , wherein the AFC comprises a calibration logic, coupled to the DCO, to generate the first control to lock a phase locked loop (PLL) prior to adjusting of the capacitor settings of the DCO by a fine amount by the second control, wherein the PLL includes the DCO. 
     
     
         15 . The apparatus of  claim 14 , wherein the AFC comprises:
 a multiplexer coupled to the DCO; and   a scaling logic coupled to a first input of the multiplexer, wherein the scaling logic is to generate the second control during a calibration mode.   
     
     
         16 . The apparatus of  claim 15 , wherein the multiplexer has a second input to receive an output of a digital low pass filter (DLPF). 
     
     
         17 . The apparatus of  claim 13 , wherein the calibration logic is to receive a reference clock (RefClk) and an output of the DCO. 
     
     
         18 . A computer platform, comprising:
 a chip having a transmitter to communicate with an off-chip receiver, the transmitter to apply a clock generated from a Phase Locked Loop (PLL) which comprises:
 a digitally controlled oscillator (LDO); 
 a first control to adjust capacitor settings of the DCO by a coarse amount; 
 a second control to adjust the capacitor settings of the DCO by a fine amount; and 
 an automatic frequency control (AFC) logic which is to provide the first and second controls such that the second control is to have an associated code which is near a middle of a range of the associated code when a temperature is to be at a mid-range value. 
   
     
     
         19 . The computer platform of  claim 18 , wherein the transmitter is part of a serial IO port. 
     
     
         20 . The computer platform of  claim 19 , wherein the serial IO port is a PCIe port. 
     
     
         21 . The computer platform of  claim 18 , wherein the AFC comprises a calibration logic, coupled to the DCO, to generate the first control to lock a phase locked loop (PLL) prior to adjusting of the capacitor settings of the DCO by a fine amount by the second control, wherein the PLL includes the DCO. 
     
     
         22 . The computer platform of  claim 21 , wherein the AFC comprises:
 a multiplexer coupled to the DCO; and   a scaling logic coupled to a first input of the multiplexer, wherein the scaling logic is to generate the second control during a calibration mode.