Computer architecture with peripherals

Abstract

A shared memory computing device that has a system interconnect, an on-chip random access memory (RAM), at least one sub-computing device and a peripheral. The RAM is connected to the system interconnect. Each sub-computing device has: (a) a first local interconnect, (b) an interconnect master connected to a local interconnect of the sub-computing device; and (c) an interconnect bridge; in which the interconnect master is adapted to issue memory transfer requests to the RAM over that bridge. The peripheral comprises a target port which is connected to the first local interconnect of the first of the at least one sub-computing devices; and a first interconnect master port which is adapted to issue memory transfer requests to the RAM. The interconnect master of the first of the at least one sub-computing devices is adapted to issue memory transfer requests to the first peripheral.

1 . A shared memory computing device comprising:
 a first system interconnect;   an on-chip random access memory store comprising at least one interconnect target port, in which the first interconnect target port is connected to the first system interconnect;   at least one sub-computing device, each sub-computing device comprising:
 a first local interconnect; 
 a first interconnect master connected to a local interconnect of the sub-computing device; 
 an interconnect bridge comprising two ports, in which:
 the first port is connected to the first system interconnect; and 
 the second port is connected to a local interconnect of the sub-computing device; and 
 
 in which the first interconnect master is adapted to issue memory transfer requests to the on-chip random access memory store; and 
   a first peripheral, comprising:
 a first interconnect target port which is connected to the first local interconnect of the first of the at least one sub-computing devices; 
 a first interconnect master port which is adapted to issue memory transfer requests to the on-chip random access memory store; 
   in which:
 the first interconnect master of the first of the at least one sub-computing devices is adapted to issue memory transfer requests to the first peripheral. 
   
     
     
         2 . A shared memory computing device as claimed in  claim 1 , in which there are at least two sub-computing devices and the first peripheral further comprises:
 a second interconnect target port which is connected to the first local interconnect of a second of the at least one sub-computing devices; and   the first interconnect master of the second of the at least two sub-computing devices is adapted to issue memory transfer requests to the first peripheral.   
     
     
         12 . A shared memory computing device as claimed in  claim 1 , in which there are at least two sub-computing devices and further comprising:
 a second peripheral, comprising a first interconnect target port which is connected to the first system interconnect;   in which the first interconnect master of at least two of the at least two sub-computing devices is adapted to issue memory transfer requests to the second peripheral.   
     
     
         3 . A shared memory computing device as claimed in  claim 2 , in which there are at least two sub-computing devices and further comprising:
 a second peripheral, comprising a first interconnect target port which is connected to the first system interconnect;   in which the first interconnect master of at least two of the at least two sub-computing devices is adapted to issue memory transfer requests to the second peripheral.   
     
     
         4 . A shared memory computing device as claimed in  claim 3 , in which the second peripheral further comprises a first interconnect master which is adapted to issue memory transfer requests to the on-chip random access memory. 
     
     
         13 . A shared memory computing device as claimed in  claim 12 , in which the second peripheral further comprises a first interconnect master which is adapted to issue memory transfer requests to the on-chip random access memory. 
     
     
         19 . A shared memory computing device as claimed in  claim 1 , further comprising a second system interconnect in which:
 the on-chip random access memory store has at least two interconnect target ports;   the second interconnect target port of the random access memory store is connected to the second system interconnect; and   the first interconnect master port of the first peripheral is connected to the second system interconnect.   
     
     
         9 . A shared memory computing device as claimed in  claim 2 , further comprising a second system interconnect in which:
 the on-chip random access memory store has at least two interconnect target ports;   the second interconnect target port of the random access memory store is connected to the second system interconnect; and   the first interconnect master port of the first peripheral is connected to the second system interconnect.   
     
     
         7 . A shared memory computing device as claimed in  claim 3 , further comprising a second system interconnect in which:
 the on-chip random access memory store has at least two interconnect target ports;   the second interconnect target port of the random access memory store is connected to the second system interconnect; and   the first interconnect master port of the first peripheral is connected to the second system interconnect.   
     
     
         5 . A shared memory computing device as claimed in  claim 4 , further comprising a second system interconnect in which:
 the on-chip random access memory store has at least two interconnect target ports;   the second interconnect target port of the random access memory store is connected to the second system interconnect; and   the first interconnect master port of the first peripheral is connected to the second system interconnect.   
     
     
         16 . A shared memory computing device as claimed in  claim 12 , further comprising a second system interconnect in which:
 the on-chip random access memory store has at least two interconnect target ports;   the second interconnect target port of the random access memory store is connected to the second system interconnect; and   the first interconnect master port of the first peripheral is connected to the second system interconnect.   
     
     
         14 . A shared memory computing device as claimed in  claim 13 , further comprising a second system interconnect in which:
 the on-chip random access memory store has at least two interconnect target ports;   the second interconnect target port of the random access memory store is connected to the second system interconnect; and   the first interconnect master port of the first peripheral is connected to the second system interconnect.   
     
     
         6 . A shared memory computing device as claimed in  claim 5 , in which the first interconnect master port of the second peripheral is connected to the second system interconnect. 
     
     
         8 . A shared memory computing device as claimed in  claim 7 , in which the first interconnect master port of the second peripheral is connected to the second system interconnect. 
     
     
         10 . A shared memory computing device as claimed in  claim 9 , in which the first interconnect master port of the second peripheral is connected to the second system interconnect. 
     
     
         15 . A shared memory computing device as claimed in  claim 14 , in which the first interconnect master port of the second peripheral is connected to the second system interconnect. 
     
     
         17 . A shared memory computing device as claimed in  claim 16 , in which the first interconnect master port of the second peripheral is connected to the second system interconnect. 
     
     
         20 . A shared memory computing device as claimed in  claim 19 , in which the first interconnect master port of the second peripheral is connected to the second system interconnect. 
     
     
         22 . A shared memory computing device as claimed in  claim 1 , in which the first system interconnect is a timeslot based interconnect. 
     
     
         11 . A shared memory computing device as claimed in  claim 2 , in which the first system interconnect is a timeslot based interconnect. 
     
     
         18 . A shared memory computing device as claimed in  claim 12 , in which the first system interconnect is a timeslot based interconnect. 
     
     
         21 . A shared memory computing device as claimed in  claim 19 , in which the first system interconnect is a timeslot based interconnect.