Computing architecture with peripherals

Abstract

A bidirectional interconnect for transporting memory transfer requests and their corresponding memory transfer responses that has: (a) a unidirectional interconnect to transport memory transfer requests; and (b) a unidirectional interconnect to transport memory transfer responses. The write memory transfer responses include at least a copy of the data to be written of the corresponding write memory transfer request. The memory transfer responses may also include a copy of the corresponding memory transfer request. This interconnect is particularly well suited for use in cache-coherent real-time computing architectures that have peripherals.

1 . A bidirectional interconnect for transporting memory transfer requests and their corresponding memory transfer responses, comprising:
 a unidirectional interconnect to transport memory transfer requests; and   a unidirectional interconnect to transport memory transfer responses, adapted to transport write memory transfer responses that includes a copy of the data to be written of the corresponding write memory transfer request.   
     
     
         2 . A bidirectional interconnect as claimed in  claim 1 , in which the unidirectional interconnect to transport memory transfer responses is further adapted to transport memory transfer responses that include a copy of the corresponding memory transfer request. 
     
     
         3 . A bidirectional interconnect as claimed in  claim 1 , in which the unidirectional interconnect to transport memory transfer responses is further adapted to transport write memory transfer responses that include a copy of the address field of the corresponding write memory transfer request. 
     
     
         4 . A bidirectional interconnect as claimed in  claim 3 , in which the unidirectional interconnect to transport memory transfer responses is further adapted to transport memory transfer responses that include a copy of the transaction type of the corresponding memory transfer request. 
     
     
         5 . A bidirectional interconnect as claimed in  claim 4 , in which the unidirectional interconnect to transport memory transfer responses is further adapted to transport write memory transfer responses that include a copy of the corresponding write memory transfer request. 
     
     
         6 . A bidirectional interconnect as claimed in  claim 5 , in which the unidirectional interconnect to transport memory transfer responses is further adapted to transport read memory transfer responses that include a copy of the corresponding read memory transfer request. 
     
     
         7 . A bidirectional interconnect as claimed in  claim 6 , in which the unidirectional interconnect to transport memory transfer responses is further adapted to transport memory transfer responses that include a copy of the corresponding memory transfer request.