Multichannel receiver

Abstract

An embodiment of the disclosed multichannel receiver may use a single master clock to generate (i) the sampling-clock signal that sets the sampling rate of the receiver's ADC and (ii) multiple electrical local-oscillator signals that are used in various channels of the receiver's analog down-converter to translate to intermediate frequency the RF signals received on the receiver's array of antennas. The multichannel receiver may employ a plurality of interconnected frequency dividers configured to variously divide the master-clock frequency to generate the sampling-clock signal and the multiple local-oscillator signals in a manner that causes these signals to have different respective frequencies.

What is claimed is: 
     
         1 . An apparatus comprising:
 a plurality of mixers, each one of the plurality of mixers being configured to mix a respective one of a plurality of electrical radio-frequency (RF) signals and a respective one of a plurality of electrical local-oscillator (LO) signals to generate a respective one of a plurality of electrical intermediate-frequency (IF) signals, each electrical LO signal of the plurality of LO signals having a different frequency;   an analog-to-digital converter (ADC) configured to convert the electrical IF signals into a corresponding digital IF signal carrying a sequence of discrete digital samples generated by the ADC at a sampling rate determined by a sampling-clock signal; and   a plurality of frequency dividers configured to frequency divide a master-clock signal to generate the sampling-clock signal and the plurality of electrical LO signals of different frequencies.   
     
     
         2 . The apparatus of  claim 1 , further comprising a first clock generator configured to generate the master-clock signal. 
     
     
         3 . The apparatus of  claim 2 , further comprising:
 a second clock generator configured to generate a digital reference-clock signal; and   a digital down-converter configured to digitally translate the digital IF signal to baseband using the digital reference-clock signal; and   wherein the first clock generator is configured to generate the master-clock signal in response to receiving the digital reference-clock signal.   
     
     
         4 . The apparatus of  claim 3 , wherein the digital down-converter is a part of a digital signal processor configured to process the digital IF signal to recover data encoded in the plurality of electrical RF signals. 
     
     
         5 . The apparatus of  claim 3 , wherein the digital down-converter comprises:
 a plurality of numerically controlled oscillators configured to generate a plurality of digital LO signals in response to receiving the digital reference-clock signal; and   a plurality of digital mixers, each configured to mix a respective portion of the digital IF signal and a respective one of the plurality of digital LO signals to generate a respective one of a plurality of digital baseband signals.   
     
     
         6 . The apparatus of  claim 1 , wherein the plurality of frequency dividers comprises two or more frequency dividers, with each of said two or more frequency dividers being configured to receive a respective copy of the master-clock signal and further configured to frequency divide the master-clock signal using a respective division factor. 
     
     
         7 . The apparatus of  claim 1 , wherein the plurality of frequency dividers comprises two or more frequency dividers that are serially connected to one another in a manner that causes a following one of the two or more frequency dividers to divide a frequency generated by a preceding one of the two or more frequency dividers. 
     
     
         8 . The apparatus of  claim 1 ,
 wherein the apparatus is configured to combine said plurality of electrical IF signals to generate a combined electrical IF signal; and   wherein the ADC is configured to convert the combined electrical IF signal into said corresponding digital IF signal carrying said sequence of discrete digital samples generated by the ADC at the sampling rate determined by the sampling-clock signal.   
     
     
         9 . The apparatus of  claim 8 , wherein the plurality of frequency dividers are further configured to divide the frequency of the master-clock signal in a manner that causes the sampling-clock signal to have a frequency that is different from any LO frequency in the plurality of electrical LO signals. 
     
     
         10 . The apparatus of  claim 1 , wherein the plurality of frequency dividers are configured to frequency divide the master-clock signal in a manner that causes the sampling-clock signal to have a frequency that is different from any LO frequency in the plurality of electrical LO signals. 
     
     
         11 . The apparatus of  claim 1 , wherein each frequency divider of the plurality of frequency dividers is configured to produce a respective one of the electrical LO signals with a respective LO frequency such that a frequency of the master-clock signal is an integer multiple of the respective LO frequency. 
     
     
         12 . The apparatus of  claim 11 , wherein the frequency dividers are configured to use integer frequency-division factors to frequency divide the master-clock signal, wherein a set of the integer frequency-division factors includes two or more consecutive integers. 
     
     
         13 . The apparatus of  claim 1 , wherein each frequency divider of the plurality of frequency dividers is configured to produce a respective one of the electrical LO signals with a respective LO frequency such that a frequency of the master-clock signal is equal to the respective LO frequency multiplied by a mixed fractional value. 
     
     
         14 . The apparatus of  claim 1 ,
 further comprising a receiver having an array of antennas; and   wherein each of the antennas is configured to generate the respective one of the plurality of electrical RF signals based on an electrical input provided by a corresponding antenna.   
     
     
         15 . The apparatus of  claim 1 , wherein the multichannel down-converter is an analog electrical circuit. 
     
     
         16 . An apparatus comprising:
 a first mixer configured to mix a first electrical radio-frequency (RF) signal and a first electrical local-oscillator (LO) signal to generate a first electrical intermediate-frequency (IF) signal;   an analog-to-digital converter (ADC) configured to convert the first electrical IF signal into a corresponding digital IF signal carrying a sequence of discrete digital samples generated by the ADC at a sampling rate determined by a sampling-clock signal;   a first clock generator configured to generate a master-clock signal;   a first frequency divider configured to frequency divide the master-clock signal to generate the first electrical LO signal; and   a second frequency divider configured to frequency divide the master-clock signal to generate the sampling-clock signal.   
     
     
         17 . The apparatus of  claim 16 , wherein the first electrical LO signal and the sampling-clock signal have different respective frequencies. 
     
     
         18 . The apparatus of  claim 16 , further comprising:
 a second mixer configured to mix a second electrical RF signal and a second electrical LO signal to generate a second electrical IF signal, wherein the ADC is further configured to convert the second electrical IF signal into a corresponding portion of the digital IF signal; and   the apparatus further comprises a third frequency divider configured to frequency divide the master-clock signal to generate the second electrical LO signal.   
     
     
         19 . The apparatus of  claim 18 , wherein the first electrical LO signal and the second electrical LO signal have different respective frequencies. 
     
     
         20 . The apparatus of  claim 16 , further comprising:
 a second clock generator configured to generate a digital reference-clock signal; and   a digital down-converter configured to digitally translate the digital IF signal to baseband using the digital reference-clock signal; and   wherein the first clock generator is configured to generate the master-clock signal in response to receiving the digital reference-clock signal.