Finfet semiconductor devices with stressed channel regions

Abstract

A FinFET device includes a substrate, a gate structure positioned above the substrate, and sidewall spacers positioned adjacent to the gate structure. An epi semiconductor material is positioned in source and drain regions of the FinFET device and laterally outside of the sidewall spacers. A fin extends laterally under the gate structure and the sidewall spacers in a gate length direction of the FinFET device, wherein the end surfaces of the fin abut and engage the epi semiconductor material. A stressed material is positioned in a channel cavity located below the fin, above the substrate, and laterally between the epi semiconductor material, the stressed material having a top surface that abuts and engages a bottom surface of the fin, a bottom surface that abuts and engages the substrate, and end surfaces that abut and engage the epi semiconductor material.

What is claimed: 
     
         1 . A FinFET device, comprising:
 a substrate comprising a first semiconductor material;   a gate structure positioned above said substrate;   sidewall spacers positioned adjacent to said gate structure;   an epi semiconductor material positioned in source and drain regions of said FinFET device and laterally outside of said sidewall spacers, said epi semiconductor material comprising a second semiconductor material;   a fin extending laterally under said gate structure and said sidewall spacers in a gate length direction of said FinFET device, wherein end surfaces of said fin abut and engage said epi semiconductor material; and   a stressed material positioned in a channel cavity that is located below said fin, above said substrate, and laterally between said epi semiconductor material, said stressed material having a top surface that abuts and engages a bottom surface of said fin, a bottom surface that abuts and engages said substrate, and end surfaces that abut and engage said epi semiconductor material.   
     
     
         2 . The FinFET device of  claim 1 , wherein said stressed material comprises a stressed semiconductor material. 
     
     
         3 . The FinFET device of  claim 1 , wherein said stressed material comprises one of a nitride material, an oxide material, and a metal-containing material. 
     
     
         4 . The FinFET device of  claim 1 , wherein said stressed material is one of a tensile-stressed material and a compressive-stressed material. 
     
     
         5 . The FinFET device of  claim 1 , wherein said substrate is silicon and said epi semiconductor material is silicon/germanium. 
     
     
         6 . The FinFET device of  claim 1 , wherein said fin comprises said first semiconductor material. 
     
     
         7 . The FinFET device of  claim 1 , wherein said first semiconductor material is different from said second semiconductor material. 
     
     
         8 . The FinFET device of  claim 1 , wherein said gate structure comprises a gate insulation layer comprising a high-k insulating material and a gate electrode comprising at least one layer of metal. 
     
     
         9 . A FinFET device, comprising:
 a lower fin structure defined in a substrate, said lower fin structure comprising a first semiconductor material;   an upper fin structure positioned above said lower fin structure, wherein said upper fin structure has opposing end surfaces and a bottom surface that is separated from a top surface of said lower fin structure by a channel cavity that extends in a gate length direction of said FinFET device between source and drain regions thereof, said upper fin structure comprising a second semiconductor material;   a gate structure positioned above and around said upper fin structure;   an epi semiconductor material positioned in each of said source and drain regions of said FinFET device and comprising a third semiconductor material, wherein said opposing end surfaces of said upper fin structure abut and engage said epi semiconductor material; and   a stressed material positioned in said channel cavity, said stressed material having a top surface that abuts and engages said bottom surface of said upper fin structure, a bottom surface that abuts and engages said top surface of said lower fin structure, and opposing end surfaces that abut and engage said epi semiconductor material.   
     
     
         10 . The FinFET device of  claim 9 , further comprising sidewall spacers positioned adjacent to said gate structure, wherein said upper fin structure and said stressed material extend laterally under said sidewall spacers, and wherein said epi semiconductor material is positioned laterally adjacent to and outside of said sidewall spacers. 
     
     
         11 . The FinFET device of  claim 9 , wherein said stressed material comprises a stressed semiconductor material. 
     
     
         12 . The FinFET device of  claim 9 , wherein said stressed material comprises one of a nitride material, an oxide material, and a metal-containing material. 
     
     
         13 . The FinFET device of  claim 9 , wherein said stressed material is one of a tensile-stressed material and a compressive-stressed material. 
     
     
         14 . The FinFET device of  claim 9 , wherein said first semiconductor material is silicon and said third semiconductor material is silicon/germanium. 
     
     
         15 . The FinFET device of  claim 9 , wherein said first and second semiconductor materials are a same semiconductor material. 
     
     
         16 . The FinFET device of  claim 9 , wherein said first semiconductor material is different from said third semiconductor material. 
     
     
         17 . The FinFET device of  claim 9 , wherein said gate structure comprises a gate insulation layer comprising a high-k insulating material and a gate electrode comprising at least one layer of metal.