Semiconductor Devices and Methods for Manufacturing the Same

Abstract

A semiconductor device includes a substrate including first and second active patterns thereon, a first gate electrode intersecting the first and second active patterns, first and second source/drain regions on the first and second active patterns, respectively, at one side of the first gate electrode, and an active contact on the first source/drain region so as to be electrically connected to the first source/drain region. The active contact includes a first sub-contact and a second sub-contact. The second sub-contact includes a vertical extension vertically extending toward the substrate. A bottom surface of the vertical extension is lower than a bottom surface of the first sub-contact.

1 . A semiconductor device comprising:
 a substrate including first and second active patterns formed thereon, the first and second active patterns extending in a first direction parallel to a top surface of the substrate;   a first gate electrode intersecting the first and second active patterns, the first gate electrode extending in a second direction intersecting the first direction;   first and second source/drain regions provided in upper portions of the first and second active patterns, respectively, at one side of the first gate electrode, wherein the first and second source/drain regions are spaced apart from each other in the second direction; and   an active contact on the first source/drain region and electrically connected to the first source/drain region,   wherein the active contact comprises: a first sub-contact overlapping with the first source/drain region in plan view; and a second sub-contact provided between the first and second source/drain regions in plan view,   wherein the second sub-contact includes a vertical extension vertically extending toward the substrate, and   wherein a bottom surface of the vertical extension extends toward the substrate beyond a bottom surface of the first sub-contact.   
     
     
         2 . The semiconductor device of  claim 1 , further comprising:
 device isolation layers disposed in the substrate to define the first and second active patterns; and   an interlayer insulating layer on the first and second source/drain regions and sidewalls of the first gate electrode,   wherein the bottom surface of the vertical extension is disposed at a level between a top surface of the interlayer insulating layer and top surfaces of the device isolation layers.   
     
     
         3 . The semiconductor device of  claim 1 , wherein a top surface of the second sub-contact is substantially coplanar with a top surface of the first sub-contact. 
     
     
         4 . The semiconductor device of  claim 1 , wherein the first sub-contact and the second sub-contact include a same material and are directly connected to each other to define one body. 
     
     
         5 . The semiconductor device of  claim 1 , wherein the vertical extension overlaps with the first sub-contact in plan view. 
     
     
         6 . The semiconductor device of  claim 2 , wherein the top surface of the interlayer insulating layer is substantially coplanar with a top surface of the first gate electrode. 
     
     
         7 . The semiconductor device of  claim 1 , further comprising:
 first and second conductive connection patterns on the first and second source/drain regions and electrically connected to the first and second source/drain regions, respectively,   wherein the first sub-contact is on a top surface of the first conductive connection pattern and is electrically connected to the first source/drain region through the first conductive connection pattern, and   wherein the second sub-contact is provided between the first and second conductive connection patterns and is spaced apart from sidewalls thereof.   
     
     
         8 . The semiconductor device of  claim 7 , further comprising:
 a barrier layer on sidewalls and a bottom surface of the active contact,   wherein a portion of the barrier layer is between the first sub-contact and the first conductive connection pattern.   
     
     
         9 . The semiconductor device of  claim 1 , further comprising:
 a second gate electrode intersecting the first and second active patterns, the second gate electrode extending in parallel to the first gate electrode,   wherein the first and second gate electrodes are spaced apart from each other in the first direction, and   wherein the active contact is provided between the first and second gate electrodes in plan view.   
     
     
         10 . The semiconductor device of  claim 9 , further comprising:
 a capping layer on top surfaces of the first and second gate electrodes,   wherein the bottom surface of the vertical extension extends toward the substrate beyond a bottom surface of the capping layer.   
     
     
         11 - 21 . (canceled) 
     
     
         22 . A semiconductor device comprising:
 a substrate;   device isolation layers disposed in the substrate to define active patterns, the active patterns including upper portions protruding from top surfaces of the device isolation layers;   a gate electrode intersecting the active patterns;   a source/drain region provided in the upper portion of at least one of the active patterns, the source/drain region adjacent to the gate electrode; and   an active contact disposed on the source/drain region and electrically connected to the source/drain region,   wherein the active contact is spaced apart from the gate electrode, and   wherein the active contact includes a vertical extension having a bottom surface lower than a top surface of the gate electrode relative to the substrate.   
     
     
         23 . The semiconductor device of  claim 22 , wherein the active contact comprises:
 a first sub-contact overlapping with the source/drain region in plan view; and   a second sub-contact directly on the first sub-contact,   wherein a top surface of the first sub-contact is substantially coplanar with a top surface of the second sub-contact,   wherein a portion of the second sub-contact, which vertically extends toward the substrate, corresponds to the vertical extension.   
     
     
         24 . The semiconductor device of  claim 23 , wherein the vertical extension overlaps with the first sub-contact in plan view. 
     
     
         25 - 28 . (canceled) 
     
     
         29 . A semiconductor device, comprising:
 a substrate including active patterns extending in parallel thereon;   a gate electrode extending across the active patterns;   respective source/drain regions in the active patterns at opposite sides of the gate electrode; and   respective active contacts electrically contacting the respective source/drain regions, wherein at least one of the respective active contacts comprises:
 a first sub-contact extending on a corresponding one of the respective source/drain regions opposite the substrate; and 
 a second sub-contact extending toward the substrate beyond the first sub-contact and between adjacent ones of the active patterns, 
   wherein the second sub-contact is separated from the adjacent ones of the active patterns by an insulating material.   
     
     
         30 . The semiconductor device of  claim 29 , further comprising:
 respective conductive connection patterns between the respective source/drain regions and the respective active contacts thereon, wherein the respective conductive connection patterns and the respective active contacts comprise different materials, and   wherein the second sub-contact of the at least one of the respective active contacts extends towards the substrate between ones of the respective conductive connection patterns on the adjacent ones of the active patterns and is separated from sidewalls of the ones of the respective conductive connection patterns by the insulating material.   
     
     
         31 . The semiconductor device of  claim 30 , wherein respective upper surfaces of the first and second sub-contacts opposite the substrate are coplanar, and wherein the first and second sub-contacts of the at least one of the respective active contacts define a unitary member. 
     
     
         32 . The semiconductor device of  claim 31 , further comprising:
 device isolation layers on the substrate between the active patterns,   wherein the insulating material comprises an interlayer insulating layer on the device isolation layers, wherein the second sub-contact of the at least one of the respective active contacts extends towards the substrate beyond a surface of the gate electrode and into the interlayer insulating layer but is confined above the device isolation layers, and wherein the first sub-contact of the at least one of the respective active contacts is confined above the surface of the gate electrode.   
     
     
         33 . The semiconductor device of  claim 32 , further comprising:
 a conductive via on the respective upper surfaces of the first and/or second sub-contacts of the at least one of the respective active contacts, wherein the via is between ones of the active patterns in plan view; and   a conductive line on the conductive via and electrically connected to the at least one of the respective active contacts thereby.   
     
     
         34 . The semiconductor device of  claim 29 , wherein the respective active contacts have coplanar surfaces, and wherein another of the respective active contacts comprises the first sub-contact but is free of the second sub-contact. 
     
     
         35 . The semiconductor device of  claim 34 , wherein the first sub-contact of the at least one of the respective active contacts extends parallel to the gate electrode, and wherein the second sub-contact of the at least one of the respective active contacts extends perpendicular to the gate electrode and parallel to the active patterns in plan view.