Semiconductor memory device

Abstract

A semiconductor memory device which includes a memory cell including two or more sub memory cells is provided. The sub memory cells each including a word line, a bit line, a first capacitor, a second capacitor, and a transistor. In the semiconductor device, the sub memory cells are stacked in the memory cell; a first gate and a second gate are formed with a semiconductor film provided therebetween in the transistor; the first gate and the second gate are connected to the word line; one of a source and a drain of the transistor is connected to the bit line; the other of the source and the drain of the transistor is connected to the first capacitor and the second capacitor; and the first gate and the second gate of the transistor in each sub memory cell overlap with each other and are connected to each other.

1 . (canceled) 
     
     
         2 . A semiconductor device comprising:
 an oxide semiconductor layer over a substrate;   a first insulating layer over the oxide semiconductor layer; and   a first electrode over the oxide semiconductor layer with the first insulating layer interposed therebetween,   wherein the oxide semiconductor layer comprises indium, gallium and zinc,   wherein the first electrode covers a side surface and a top surface of the oxide semiconductor layer with the first insulating layer interposed therebetween.   
     
     
         3 . The semiconductor device according to  claim 2 , wherein the first insulating layer comprises gallium. 
     
     
         4 . The semiconductor device according to  claim 2 , further comprising:
 a second electrode and a second insulating layer between the substrate and the oxide semiconductor layer,   wherein the second electrode overlaps with the oxide semiconductor layer with the second insulating layer interposed therebetween.   
     
     
         5 . The semiconductor device according to  claim 4 , wherein the second insulating layer comprises gallium. 
     
     
         6 . The semiconductor device according to  claim 2 , further comprising a capacitor, wherein the capacitor comprises the oxide semiconductor layer. 
     
     
         7 . The semiconductor device according to  claim 6 , wherein one of electrodes of the capacitor is the oxide semiconductor layer. 
     
     
         8 . A semiconductor device comprising:
 a transistor comprising:   an oxide semiconductor layer over a substrate;   a first gate insulating layer over the oxide semiconductor layer; and   a first gate electrode over the oxide semiconductor layer with the first gate insulating layer interposed therebetween,   wherein the oxide semiconductor layer comprises indium, gallium and zinc,   wherein the transistor comprises a channel formation region in the oxide semiconductor layer, and   wherein in a cross-section in a channel width direction, the first gate electrode covers a side surface and a top surface of the oxide semiconductor layer with the first gate insulating layer interposed therebetween.   
     
     
         9 . The semiconductor device according to  claim 8 , further comprising:
 a second gate electrode and a second gate insulating layer between the substrate and the oxide semiconductor layer,   wherein the second gate electrode overlaps with the oxide semiconductor layer with the second gate insulating layer interposed therebetween.   
     
     
         10 . The semiconductor device according to  claim 9 , wherein the first gate electrode and the second gate electrode overlap with each other and are electrically connected to each other. 
     
     
         11 . The semiconductor device according to  claim 8 , wherein the oxide semiconductor layer comprises impurity regions provided so as to sandwich the channel formation region, and a source electrode and a drain electrode are connected to the impurity regions. 
     
     
         12 . The semiconductor device according to  claim 8 , further comprising a capacitor, wherein the capacitor comprises the oxide semiconductor layer. 
     
     
         13 . The semiconductor device according to  claim 12 , wherein one of electrodes of the capacitor is the oxide semiconductor layer.