Inductor assembly and method of using same

Abstract

An inductor assembly generally comprises at least one helical inductive component comprising that includes a plurality of conductive line layers having conductive lines therein. A plurality of vias are configured to couple conductive lines from two or more conductive line layers such that a spacing between two adjacent parallel conductive lines, in different conductive line layers from each other, is two or more times a distance between respective bottom surfaces of two adjacent conductive line layers.

What is claimed is: 
     
         1 . An integrated circuit comprising:
 a semiconductor substrate ;   at least one helical inductive component including a plurality of dielectric layers above the semiconductor substrate, the plurality of dielectric layers containing therein:   a plurality of conductive line layers having conductive lines , wherein each of the plurality of conductive line layers comprises a pair of conductive lines parallel to each other and perpendicular to a pair of conductive lines in a next adjacent conductive line layer; and   a plurality of vias configured to couple said conductive lines of adjacent layers from two or more of said plurality of conductive line layers such that a smallest spacing between two adjacent parallel conductive lines aligned one above the other, in different conductive line layers from each other, is two or more times a distance between respective bottom surfaces of two adjacent conductive line layers of said plurality of conductive line layers.   
     
     
         2 . The integrated circuit of  claim 1 , wherein each conductive line in a first one of the plurality of conductive line layers is connected in series with an adjacent conductive line in a second one of the plurality of conductive line layers. 
     
     
         3 . The integrated circuit of  claim 2 , wherein each conductive line in the first one of the plurality of conductive line layers is perpendicular to the adjacent conductive line in the second one of the plurality of conductive line layers. 
     
     
         4 . The integrated circuit of  claim 3 , wherein the at least one helical inductive component has a plurality of windings, and a vertical direction of the at least one helical inductive component reverses twice in each winding. 
     
     
         5 . The integrated circuit of  claim 1 , wherein said at least one helical inductive component comprises a first helical inductive component being arranged according to a first layout and said second helical inductive component being arranged according to a second layout. 
     
     
         6 . The integrated circuit of  claim 5 , wherein said first helical inductive component substantially surrounds said second helical inductive component. 
     
     
         7 . The integrated circuit of  claim 5 , further comprising a center tap between said first helical inductive component and said second helical inductive component for applying a bias voltage. 
     
     
         8 . The integrated circuit of  claim 5 , wherein the first layout is rotated with respect to the second layout. 
     
     
         9 . An integrated circuit (IC) comprising:
 a semiconductor substrate;   at least one helical inductive component including a plurality of dielectric layers above the semiconductor substrate, the plurality of dielectric layers containing therein:   a first conductive line layer having a first line and a third line parallel to each other, and a second line joining an end of the first line to an end of the second line;   a second conductive line layer having a fourth line parallel to the second line, a fifth line (no number) parallel to the third line , and a sixth line (no number) parallel to the fourth line , the fifth line joining an end of the fourth line to an end of the sixth line; and   a via layer having a first via connecting the first line and the second line to the fourth line, a second via connecting the second line and the third line to the fourth line and fifth line, and a third via connecting the third line to the fifth and sixth lines.   
     
     
         10 . The IC of  claim 9 , wherein the second line, the fourth line, the first via and the second via form a first rectangle perpendicular to the first and second conductive line layers. 
     
     
         11 . The IC of  claim 10 , wherein the third line, the fifth line, the second via and the third via form a second rectangle perpendicular to the first and second conductive line layers. 
     
     
         12 . The IC of  claim 11 , wherein the second rectangle is perpendicular to the first rectangle. 
     
     
         13 . The IC of  claim 12 , wherein the first line, second line, third line, fourth line, fifth line, sixth line, first via, second via and third via form a first winding, the IC further comprising:
 a second winding having a same layout as the first winding, the second winding located in different layers from the first winding; and   a via connecting the first winding and the second winding in series.   
     
     
         14 . An integrated circuit (IC) comprising:
 a semiconductor substrate;   a plurality of dielectric layers above the semiconductor substrate, the plurality of dielectric layers containing a helical inductive component  106  having a plurality of windings therein, each of the plurality of windings comprising:   a first conductive line layer having a first conductive line, and a second conductive line parallel to each other;   a second conductive line layer having a third conductive line and a fourth conductive line, the third and fourth conductive lines perpendicular to the first and second conductive lines;   a first via connecting the first and third conductive lines;   a second via connecting the third and second conductive lines;   a third via connecting the second and fourth conductive lines; and   a fourth via connecting the fourth conductive line to another one of the plurality of windings, wherein each pair of adjacent windings that are parallel to each other are separated from each other by at least twice a distance between respective bottom surfaces of the first and second conductive line layers.   
     
     
         15 . The integrated circuit of  claim 14 , wherein said helical inductive component is arranged according to a first layout; and
 said IC further comprises a second helical inductive component arranged according to a second layout.   
     
     
         16 . The integrated circuit of  claim 15 , further comprising positioning a center tap between the helical inductive component and the second helical inductive component for applying a bias voltage. 
     
     
         17 . The integrated circuit of  claim 15 , wherein the first layout is rotated with respect to the second layout. 
     
     
         18 . The integrated circuit of  claim 15 , further comprising a center tap between said helical inductive component and said second helical inductive component. 
     
     
         19 . The integrated circuit of  claim 15 , wherein the helical inductive component and the second helical inductive component are located side-by-side. 
     
     
         20 . The integrated circuit of  claim 15 , wherein the second helical inductive component has a plurality of windings and a plurality of switches connected to respective ones of the windings, the switches connected to a common connecting path.