Solid-state drive with non-volatile random access memory

Abstract

A solid-state drive includes a flash memory device, a power loss protection circuit, a dynamic random access memory (RAM) coupled to the power loss protection circuit, and a controller configured to direct I/O requests to either the flash memory drive or the RAM. Because the controller can direct I/O request to the RAM, the RAM is revealed as a separate mass storage device to a host. Consequently, the RAM provides additional and significantly higher performance storage capacity to the solid-state drive.

We claim: 
     
         1 . A data storage device comprising:
 a flash memory device;   a volatile random access memory (RAM) that is coupled to a power loss protection circuit; and   a controller configured to store a mapping table that maps a first portion of logical block addresses (LBAs) to respective physical locations in the flash memory device and a second portion of the LBAs to respective physical locations in the RAM, and perform read and write operations using the mapping table.   
     
     
         2 . The data storage device of  claim 1 , wherein the controller is further configured to, in response to receiving a power loss indication from the power loss protection circuit, copy data that are associated with the second portion of the LBAs and stored in the respective physical locations in the RAM to a reserved region of the flash memory device. 
     
     
         3 . The data storage device of  claim 2 , wherein the controller is further configured to, prior to receiving the power loss indication, maintain an available storage capacity of the reserved region that is as large as a storage capacity of the physical locations in the RAM that are mapped by the second portion of the LBAs. 
     
     
         4 . The data storage device of  claim 2 , wherein the reserved region comprises erased data storage blocks of the flash memory device. 
     
     
         5 . The data storage device of  claim 1 , wherein the RAM includes a first region in which system data and the mapping table are stored and a second region to which the second portion of the LBAs is mapped. 
     
     
         6 . The data storage device of  claim 1 , wherein the controller is further configured to receive data from a computing device external to the data storage device via one of an Ethernet, a serial advanced technology attachment (SATA), a serial attached small computer system interface (SAS), a small computer system interface (SCSI), or a peripheral component interconnect express (PCIe) connection. 
     
     
         7 . The data storage device of  claim 1 , wherein the power loss protection circuit comprises a management circuit and a temporary power source sized to power the controller, the flash memory device, and the RAM for a time sufficient for the controller to copy data that are associated with the second portion of the plurality of LBAs and stored in the physical locations in the RAM to physical locations in a reserved region of the flash memory device. 
     
     
         8 . The data storage device of  claim 1 , wherein the temporary power source comprises a supercapacitor. 
     
     
         9 . The data storage device of  claim 1 , wherein the flash memory device, the RAM, the controller, and the power loss protection circuit are all mounted on a single printed circuit board. 
     
     
         10 . The data storage device of  claim 1 , wherein the controller is configured to store the mapping table in the RAM. 
     
     
         11 . In a data storage device that includes a flash memory device, a volatile random access memory (RAM) device, and a controller, all coupled to a power loss protection circuit, a method of retrieving data from the data storage device, the method comprising:
 receiving from a computing device external to the data storage device a read command that references a logical block address (LBA);   based on the LBA, determining a physical location in the RAM;   reading a set of data from the determined physical location in the RAM; and   transmitting the read data to the computing device.   
     
     
         12 . The method of  claim 12 , wherein determining the physical location in the RAM comprises consulting a mapping table that establishes a one-to-one correspondence between a plurality of LBAs and respective physical locations in the RAM. 
     
     
         13 . The method of  claim 12 , wherein the mapping table is stored in the RAM. 
     
     
         14 . The method of  claim 12 , wherein the plurality of LBAs are associated with the computing device. 
     
     
         15 . The method of  claim 12 , wherein the mapping table further establishes a one-to-one correspondence between a plurality of LBAs and respective physical locations in the flash memory device. 
     
     
         16 . The method of  claim 12 , wherein the read command is received from the computing device via one of an Ethernet, a serial advanced technology attachment (SATA), a serial attached small computer system interface (SAS), a small computer system interface (SCSI), or a peripheral component interconnect express (PCIe) connection. 
     
     
         17 . In a data storage device that includes a flash memory device, a volatile random access memory (RAM), and a controller, all coupled to a power loss protection circuit, a method of storing data, the method comprising:
 receiving from a computing device external to the data storage device a write command that includes a set of data and references a logical block address (LBA);   writing the set of data to a physical location in the RAM; and   updating an entry in a mapping table to indicate a one-to-one correspondence between the LBA and the physical location in the RAM.   
     
     
         18 . The method of  claim 17 , wherein the mapping table is stored in the RAM. 
     
     
         19 . The method of  claim 17 , wherein the mapping table establishes a one-to-one correspondence between a plurality of LBAs and respective physical locations in the RAM. 
     
     
         20 . The method of  claim 17 , further comprising maintaining an available storage capacity of a reserved region in the flash memory device that is sufficient to store data that are stored in physical locations in the RAM and are associated with LBAs in the mapping table.