Power reduction in bus interconnects

Abstract

In one form, power consumed in transmitting data over a bus interconnect is reduced. The power is reduced by configuring a buffer that is used to store data to be transmitted over the bus interconnect as a two-dimensional (2D) buffer array having a plurality of rows and columns. The data stored in the 2D buffer array is then analyzed to determine a mode of transmitting the data that uses a least amount of power. The determined mode is used to transmit the data over the bus interconnect.

1 . A method of reducing power consumption in a bus interconnect comprising:
 analyzing data stored in the a two-dimensional (2D) buffer array for transmission over the bus interconnect to determine a mode of transmitting the stored data, the determined mode being a mode using a least amount of power to transmit the stored data; and   transmitting the stored data over the bus interconnect according to the determined mode.   
     
     
         2 . The method of  claim 1 , wherein the determined mode includes transmitting the stored data one column at a time. 
     
     
         3 . The method of  claim 1 , wherein the determined mode includes transmitting the stored data one row at a time. 
     
     
         4 . The method of  claim 1 , wherein the stored data is encoded using an encoding algorithm. 
     
     
         5 . The method of  claim 1 , wherein the buffer is configured as a three-dimensional (3D) buffer array having three planes, wherein the determined mode includes transmitting the stored data in the 3D buffer array from one plane of the three planes, the one plane being a plane using the least amount of power to transmit the data. 
     
     
         6 . A circuit comprising:
 a buffer for storing data; and   a controller, wherein the controller:
 analyzes N bits data chunks to determine a mode of transmitting the data in the buffer that uses a least amount of power; and 
 transmits the data in the buffer according to the determined mode. 
   
     
     
         7 . The circuit of  claim 6 , wherein the controller configures the buffer into an N×N buffer array. 
     
     
         8 . The circuit of  claim 7 , wherein the determined mode includes transmitting the data in the N×N buffer array one column at a time. 
     
     
         9 . The circuit of  claim 7 , wherein the determined mode includes transmitting the data in the N×N buffer array one row at a time. 
     
     
         10 . The circuit of  claim 6 , wherein analyzing the N bits data chunks includes determining whether to encode the N bits data chunks using an encoding algorithm. 
     
     
         11 . The circuit of  claim 10 , wherein the N bits chunks of data is encoded using the encoding algorithm. 
     
     
         12 . The circuit of  claim 6 , further comprising a control data line, wherein the controller uses the control data line to notify a receiving circuit of the determined mode of transmitting the data. 
     
     
         13 . The circuit of  claim 12 , wherein a command bus comprises the control data line. 
     
     
         14 . The circuit of  claim 6 , wherein the data is transmitted over an interconnect bus to a receiving circuit, wherein the buffer and the controller are included in a first integrated circuit and the receiving circuit is included in a second integrated circuit. 
     
     
         15 . The circuit of  claim 14 , wherein the buffer, the controller and the receiving circuit are included in an integrated circuit. 
     
     
         16 . The circuit of  claim 6 , wherein the circuit is in a data processing device. 
     
     
         17 . The circuit of  claim 6 , wherein the circuit is in a memory device. 
     
     
         18 . A circuit comprising:
 a two-dimensional (2D) buffer array for storing data;   a data control line; and   a controller, wherein the controller:
 analyzes data in the 2D buffer array to determine a mode of transmitting the data to the receiving circuit that uses a least amount of power; 
 transmits the data in the 2D buffer array to the receiving circuit according to the determined mode; and 
 notifies the receiving circuit of the determined mode of transmitting the data using the data control line. 
   
     
     
         19 . The circuit of  claim 18 , wherein the buffer and the controller are in a first integrated circuit and the receiving circuit is in a second integrated circuit. 
     
     
         20 . The circuit of  claim 18 , wherein the buffer, the controller and the receiving circuit are in an integrated circuit. 
     
     
         21 . The method of  claim 1 , further comprising:
 configuring a buffer as the 2D buffer array having a plurality of rows and columns; and   storing data to be transmitted over the bus interconnect into the buffer.   
     
     
         22 . The circuit of  claim 6 , wherein the controller further:
 stores data to be transmitted in the buffer; and   divides the data in the buffer into a plurality of the N bits data chunks, N being an integer.   
     
     
         23 . The circuit of  claim 18 , wherein the controller further:
 configures a buffer as the 2D buffer array; and   stores data to be transmitted to a receiving circuit in the 2D buffer array.