System, apparatus, and method for n/p tuning in a fin-fet

Abstract

The n-type to p-type fin-FET strength ratio in an integrated logic circuit may be tuned by the use of cut regions in the active and dummy gate electrodes. In some examples, separate cut regions for the dummy gate electrodes and the active gate electrode may be used to allow for different lengths of gate pass-active regions resulting in appropriately tuned integrated logic circuits.

What is claimed is: 
     
         1 . A fin-FET comprising:
 an active gate electrode extending vertically a first distance ;   a first dummy gate electrode extending vertically a second distance, the first dummy gate electrode being in parallel with the active gate electrode;   a first cut region extending horizontally across the active gate electrode;   a second cut region spaced vertically from the first cut region and extending horizontally across the active gate electrode;   an active region between the first cut region and the second cut region;   a dummy gate pass-active region between an end of the first dummy gate electrode and the active region along the first dummy gate electrode; and   an active gate pass-active region between the first cut region and the active region along the active gate electrode.   
     
     
         2 . The fin-FET of  claim 1 , wherein the active gate pass-active region is one of approximately 0.326 μm, 0.1 μm, 0.042 μm, or 0.035 μm. 
     
     
         3 . The fin-FET of  claim 2 , wherein the dummy gate pass-active region is longer than the active gate pass-active region and is one of approximately 0.326 μm, 0.1 μm, 0.042 μm, or 0.035 μm. 
     
     
         4 . The fin-FET of  claim 3 , wherein the first cut region includes a first portion extending across the active gate electrode and a second portion extending across the first dummy gate electrode, the dummy gate pass-active region being between the second portion of the first cut region and the active region. 
     
     
         5 . The fin-FET of  claim 4 , wherein the first portion of the first cut region has a width smaller than a width of the second portion of the first cut region. 
     
     
         6 . The fin-FET of  claim 4 , wherein the first portion of the first cut region has a width larger than a width of the second portion of the first cut region. 
     
     
         7 . The fin-FET of  claim 4 , wherein the fin-FET is incorporated into a device selected from a group consisting of a set top box, a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer, and further including the device. 
     
     
         8 . A fin-FET comprising:
 an active gate electrode extending vertically a first distance;   a first dummy gate electrode extending vertically a second distance, the first dummy gate electrode being in parallel with the active gate electrode;   a first cut region extending horizontally across the first dummy gate electrode;   a second cut region spaced vertically from the first cut region and extending horizontally across the first dummy gate electrode;   an active region between the first cut region and the second cut region;   a dummy gate pass-active region between the first cut region and the active region along the first dummy gate electrode; and   an active gate pass-active region between an end of the active gate electrode and the active region along the active gate electrode.   
     
     
         9 . The fin-FET of  claim 8 , wherein the active gate pass-active region is one of approximately 0.326 μm, 0.1 μm, 0.042 μm, or 0.035 μm. 
     
     
         10 . The fin-FET of  claim 9 , wherein the dummy gate pass-active region is shorter than the active gate pass-active region and is one of approximately 0.326 μm, 0.1 μm, 0.042 μm, or 0.035 μm. 
     
     
         11 . The fin-FET of  claim 10 , wherein the first cut region includes a first portion extending across the active gate electrode and a second portion extending across the first dummy gate electrode, the active gate pass-active region being between the first portion of the first cut region and the active region. 
     
     
         12 . The fin-FET of  claim 11 , wherein the first portion of the first cut region has a width smaller than a width of the second portion of the first cut region. 
     
     
         13 . The fin-FET of  claim 11 , wherein the first portion of the first cut region has a width larger than a width of the second portion of the first cut region. 
     
     
         14 . The fin-FET of  claim 11 , wherein the fin-FET is incorporated into a device selected from a group consisting of a set top box, a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer, and further including the device. 
     
     
         15 . A fin-FET comprising:
 an active gate electrode extending vertically a first distance;   a first dummy gate electrode extending vertically a second distance, the first dummy gate electrode being in parallel with the active gate electrode;   a second dummy gate electrode extending in parallel with the first dummy gate electrode and spaced horizontally therefrom;   a first cut region extending horizontally across the first dummy gate electrode;   a second cut region spaced vertically from the first cut region and extending horizontally across the first dummy gate electrode;   an active region between the first cut region and the second cut region;   a dummy gate pass-active region between the first cut region and the active region along the first dummy gate electrode;   a second dummy gate pass-active region between an end of the second dummy gate electrode and the active region along the second dummy gate electrode; and   an active gate pass-active region between an end of the active gate electrode and the active region along the active gate electrode.   
     
     
         16 . The fin-FET of  claim 15 , wherein the active gate pass-active region is one of approximately 0.326 μm, 0.1 μm, 0.042 μm, or 0.035 μm. 
     
     
         17 . The fin-FET of  claim 16 , wherein the dummy gate pass-active region is shorter than the active gate pass-active region and is one of approximately 0.326 μm, 0.1 μm, 0.042 μm, or 0.035 μm. 
     
     
         18 . The fin-FET of  claim 17 , wherein the second dummy gate pass-active region is approximately equal to the active gate pass-active region. 
     
     
         19 . The fin-FET of  claim 18 , wherein the first cut region includes a first portion extending across the active gate electrode and a second portion extending across the first dummy gate electrode, the active gate pass-active region being between the first portion of the first cut region and the active region. 
     
     
         20 . The fin-FET of  claim 19 , wherein the first portion of the first cut region has a width smaller than a width of the second portion of the first cut region. 
     
     
         21 . The fin-FET of  claim 19 , wherein the first portion of the first cut region has a width larger than a width of the second portion of the first cut region. 
     
     
         22 . The fin-FET of  claim 19 , wherein the first portion of the first cut region extends across the second dummy gate electrode, the second dummy gate pass-active region being between the first portion of the first cut region and the active region. 
     
     
         23 . The fin-FET of  claim 19 , wherein the fin-FET is incorporated into a device selected from a group consisting of a set top box, a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer, and further including the device. 
     
     
         24 . A fin-FET comprising:
 an active gate electrode extending vertically a first distance;   a first dummy gate electrode extending vertically a second distance, the first dummy gate electrode being in parallel with the active gate electrode;   a first cut region extending horizontally across the active gate electrode and the first dummy gate electrode;   a second cut region spaced vertically from the first cut region and extending horizontally across the active gate electrode and the first dummy gate electrode;   an active region between the first cut region and the second cut region;   a dummy gate pass-active region between the first cut region and the active region along the first dummy gate electrode; and   an active gate pass-active region between the first cut region and the active region along the active gate electrode.   
     
     
         25 . The fin-FET of  claim 24 , wherein the active gate pass-active region is approximately equal in length to the dummy gate pass-active region. 
     
     
         26 . The fin-FET of  claim 24 , wherein the active gate pass-active region is one of approximately 0.326, 0.1, 0.042, or 0.035. 
     
     
         27 . The fin-FET of  claim 26 , wherein the dummy gate pass-active region is different than the active gate pass-active region and is one of approximately 0.326, 0.1, 0.042, or 0.035. 
     
     
         28 . The fin-FET of  claim 27 , wherein the fin-FET is incorporated into a device selected from a group consisting of a set top box, a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer, and further including the device.