Method of Manufacturing a Semiconductor Device Having a Buried Channel/Body Zone

Abstract

A method of manufacturing a semiconductor device includes etching cavities into a semiconductor layer by crystallographic etching having an etch rate that depends upon an orientation of crystal planes, wherein a transistor fin is formed between two of the cavities at a distance to a first surface of the semiconductor layer, forming a channel/body zone of a transistor cell in the transistor fin, and forming source zones and drain regions of the transistor cell in the semiconductor layer, wherein junctions between the channel/body zone and the source zones as well as the drain regions are formed at a distance to the first surface.

What is claimed is: 
     
         1 . A method of manufacturing a semiconductor device, the method comprising:
 etching cavities into a semiconductor layer by crystallographic etching having an etch rate that depends upon an orientation of crystal planes, wherein a transistor fin is formed between two of the cavities at a distance to a first surface of the semiconductor layer;   forming a channel/body zone of a transistor cell in the transistor fin; and   forming source zones and drain regions of the transistor cell in the semiconductor layer, wherein junctions between the channel/body zone and the source zones as well as the drain regions are formed at a distance to the first surface.   
     
     
         2 . The method of  claim 1 , further comprising:
 forming first gate sections in the cavities on opposing sides of the transistor fin.   
     
     
         3 . The method of  claim 1 , further comprising:
 forming separation trenches between electrode fins, wherein the cavities extend from a bottom of the separation trenches into the semiconductor layer and the source zones and drain regions are formed in portions of the electrode fins.   
     
     
         4 . The method of  claim 3 , wherein a plurality of transistor fins is formed between each pair of electrode fins. 
     
     
         5 . The method of  claim 1 , further comprising:
 forming a gate dielectric covering exposed surfaces of the transistor fins before providing the gate electrode.   
     
     
         6 . The method of  claim 5 , further comprising:
 widening the cavities before forming the gate dielectric or the first gate sections.   
     
     
         7 . The method of  claim 1 , wherein the junctions between the channel/body zones and the source zones and the channel/body zones and the drain regions are parallel to the first surface. 
     
     
         8 . The method of  claim 1 , further comprising:
 forming a conformal mask liner covering the transistor fins before forming the cavities; and   opening locally the conformal mask liner before forming the cavities to form a mask liner mask.   
     
     
         9 . The method of  claim 8 , further comprising:
 removing the mask liner mask after the crystallographic etching.