Branch look-ahead instruction disassembling, assembling, and delivering system apparatus and method for microprocessor system

Abstract

A method and system of the branch look-ahead (BLA) instruction disassembling, assembling, and delivering are designed for improving speed of branch prediction and instruction fetch of microprocessor systems by reducing the amount of clock cycles required to deliver branch instructions to a branch predictor located inside the microprocessors. The invention is also designed for reducing run-length of the instructions found between branch instructions by disassembling the instructions in a basic block as a BLA instruction and a single or plurality of non-BLA instructions from the software/assembly program. The invention is also designed for dynamically reassembling the BLA and the non-BLA instructions and delivering them to a single or plurality of microprocessors in a compatible sequence. In particular, the reassembled instructions are concurrently delivered to a single or plurality of microprocessors in a timely and precise manner while providing compatibility of the software/assembly program.

What is claimed is: 
     
         1 . An apparatus for producing a branch look-ahead (BLA) instruction disassembling, assembling, and delivering system comprising:
 a BLA instruction/non-BRA instruction (BI/non-BI) disassembling system;   a single or plurality of dynamic BI/non-BI assembling and delivering systems; and   a single or plurality of backend microprocessors; wherein the apparatus for producing the BI disassembling, assembling, and delivering system is operable to:
 identify each BI comprising an entire or a part of the basic block with or without including a branch or flow control instruction required to be predicted by a branch predictor, from a software and/or assembly program for generating BI program and non-BI program wherein the basic block is an instruction segment with only one entry and only one exit in the program; 
 compose BI program comprising BIs and/or some non-BIs with additional information to access a single or plurality of the non-BIs associated to each BI if necessary; 
 deliver the BIs from the BI program to a single or plurality of the microprocessors according to the BI fetch order while delivering the non-BIs from the non-BI program to the microprocessors according to the non-BI fetch order obtained from the associated BI; 
 deliver a single or plurality of BIs to the branch predictor for predicting a single or plurality of locations of the next BIs in the BI program and start to deliver the next BIs to the microprocessors while continuous delivering the non-BIs associated the previous or current BIs delivered to the microprocessors; and 
 produce a single or plurality of branch prediction results of the BIs before completely fetching the non-BIs of the associate BIs; 
 where in the BI disassembling, assembling, and delivering system is further operable to:
 disassemble NIs in a software and/or assembly program to BI program and non-BI program; 
 compose a BI comprising a single or plurality of another BIs and/or non-disassembled NIs; 
 compose a single or plurality of BIs representing a single or plurality of levels of loops in the software and/or assembly program; 
 compose a non-BI comprising a single or plurality of another non-BIs and/or non-disassembled NIs; 
 compose a single or plurality of non-BIs representing a single or plurality of levels of loops in the software and/or assembly program; 
 assign BIs and non-BIs to the sequentially and/or concurrently accessible BI and non-BI main memories; 
 access BIs and non-BIs from the sequentially and/or concurrently accessible BI and non-BI main memories to the sequentially, concurrently, and/or a single or plurality of times quickly accessible BI and non-BI caches, wherein the plurality of times quickly accessible caches are two or more times faster than NI fetch speed of microprocessors; 
 assemble the NIs from the non-BI program and/or BI program during the NI fetch operation via a single or plurality of BI/non-BI prefetch/fetch systems; 
 prefetch the BIs addressed by the BI prefetch/decode units to the BI caches; 
 prefetch the BIs addressed by the BLA systems to the BI caches whenever a single or plurality of branch target addresses is obtained from a single or plurality of BLA branch prediction units in the BLA systems or a single or plurality of interrupt processing units in the backed microprocessors; 
 terminate the BI prefetch after continuously prefetching BIs from both of the predicted and non-predicted paths one or more times to the BI caches; 
 decode the prefetched BIs for prefetching the associated non-BIs and for prefetching variable-length native instructions (NIs) to the BI caches; 
 fetch the BIs addressed by the BI fetch/decode units to the BLA systems; 
 fetch the BIs addressed by the BLA systems to the BLA systems whenever a single or plurality of branch target addresses is obtained from a single or plurality of BLA branch prediction units in the BLA systems or a single or plurality of interrupt processing units in the backed microprocessors; 
 decode the fetched BIs for fetching the associated non-BIs and for fetching fixed- and/or variable-length NIs to the BLA systems; 
 forward a single or plurality of the fetched BIs to a single or plurality of BI decode units via the BI fetch units; 
 initiate the branch prediction operations of the BIs received within a single or plurality of clock cycles ahead comparing with the branch prediction operations with NIs fetched and decoded in the non-BI fetch units and the non-BI decode units by identifying any BIs required to be predicted for their branch operations and branch target locations with the branch prediction information forwarded to the BLA branch prediction units; 
 initiate next BI and non-BI prefetch and fetch operations according to the branch prediction results available to a single or plurality of clock cycles ahead for enhancing performance of the microprocessor by reducing taken-branch latencies; 
 filter BIs representing a single or plurality of loops by the BI decode units and hold further BIs fetched in the BI fetch units while reissuing the same BIs representing the same single or plurality of loops to the BAL branch prediction units; 
 eliminate recursive BI and non-BI prefetching and fetching operations from the BI/non-BI memory systems to the BRA systems via the BI/non-BI prefetch/fetch systems; 
 decode the BIs to redirect the associated non-BIs fetched to a single or plurality of non-BIQs in the non-BI fetch units if the fetched non-BIs and/or NIs in the non-BIQ are changed; 
 detect and process the disrupting operations of BI, non-BI, and/or NI fetch, decode, and/or execution orders, such as interrupts by the interrupt processing units, branch misprediction correction operations by the backend processing engines, and other parts in microprocessors; 
 store current BPCs, non-BPCs, and/or NPCs to the stacks in order to resume the disrupted operations of the BIs, non-BIs, and/or NIs; 
 update new NPC values to the BPCs in the BI fetch units and/or non-BPCs and/or NPCs in the non-BI fetch units to prefetch and/or fetch the BIs, non-BIs, and/or NIs from the disrupted locations; 
 restore NPC values of the BPCs, non-BPCs, and/or NPCs stored in the stacks to the BPCs and/or non-BPCs and/or NPCs; 
 reset a single or plurality of values of the non-BPCs and/or NPCs whenever the last NIs of the associated non-BIs are fetched; 
 increase a single or plurality of values of the non-BPCs and/or NPCs whenever non-BIs and/or NIs of the next non-BIs are fetched or whenever the first NIs of the associated non-BIs are fetched; and 
 repeat resetting and increasing the values of the non-BPCs and/or NPCs until the next non-BIs and/or the last NIs of the non-BIs are fetched. 
 
   
     
     
         2 . The apparatus for producing a BI disassembling, assembling, and delivering system of  claim 1 , wherein the BI disassembling is operable to:
 disassemble BIs from the software and/or assembly program by creating a BI for representing a segment of the NIs in continuous execution order in the program;   disassemble a single or plurality of loops from the software and/or assembly program by creating a BI for representing the single or plurality of loops;   disassemble unconditional flow control instructions including unconditional jumps, subroutine callers and/or returners from the software and/or assembly program by creating associated BIs for undisrupted BI prefetch and/or fetch;   comprise an opcode and a single or plurality of information fields containing location information of the first NI of the segment in each BI;   assign different opcodes used in the NIs found the software and/or assembly program to the BIs;   identify number of the NIs encapsulated in a BI in an additional field in the BI;   distinguish the last NI in the non-BIs assembled by the BI with assigning the different bit value of the last NI from the bit value of the other NIs and storing the associated bits and NIs in the dedicated main non-BI memory;   disassemble non-BIs from the software and/or assembly program by creating a non-BI for representing a segment of the variable-length NIs in continuous execution order in the program;   disassemble a single or plurality of loops from the software and/or assembly program by creating a non-BI for representing the single or plurality of loops comprising a single or plurality of segments of the variable-length NIs;   disassemble unconditional flow control instructions including unconditional jumps, subroutine callers and/or returners from the software and/or assembly program by creating associated non-BIs for undisrupted non-BI prefetch and/or fetch;   compose a non-BI with the NIs and associated information of the BI;   disassemble NIs representing a segment of the fixed-length NIs in continuous execution order from the software and/or assembly program; and   disassemble NIs representing a single or plurality of loops comprising the fixed-length NIs from the software and/or assembly program.   
     
     
         3 . The apparatus for producing a BI disassembling, assembling, and delivering system of  claim 1 , wherein the single or plurality of dynamic BI/non-BI assembling and delivering systems further comprises:
 a single or plurality of BI/non-BI memory systems;   a single or plurality of BI/non-BI prefetch/fetch systems; and   a single or plurality of the BLA systems;   wherein the apparatus for producing the dynamic BI/non-BI assembling and delivering systems is operable to:
 assemble the non-BI program stored in the non-BI memories via the non-BI caches according to the associated BI program stored in the BI memories and caches after delivering BIs to the BI/non-BI prefetch/fetch systems during the BI assembling and delivering time; 
 allocate the BIs and non-BIs separately to the different locations of the sequentially, concurrently, and/or a plurality of times quickly accessible caches and main memories in the BI/non-BI memory systems; 
 prefetch and/or fetch sequentially and/or concurrently the BI/non-BIs addressed by the associated BPCs and/or non-BPCs in the BI/non-BI prefetch/fetch systems via the BI and/or non-BI memory systems; 
 fetch the BIs from the locations addressed by the BPCs in the BI fetch/decode units whenever the associated BPCs in the BI fetch/decode units are updated with new NPC values by decoding the fetched BI with the BI fetch/decode units; 
 fetch the BIs from the locations received by the NPC values from the BLA systems whenever a single or plurality of branch target addresses is obtained via the BLA branch prediction units; 
 fetch the BIs from the locations addressed by the interrupt processing units in the backed microprocessors; 
 fetch variable-length NIs from the NPC values stored in the NPCs in the non-BI fetch units; 
 provide a single or plurality of new non-BPC values for fetching the associated non-BIs to the non-BI fetch units and to non-BPCs by decoding the fetched BIs; 
 store the non-BIs in the sequentially, concurrently, and/or a plurality of times quickly accessible a single or plurality of caches and main memories; 
 prefetch the non-BIs from the locations addressed by the program counters in the non-BI prefetch units whenever the associated BIs are prefetched by the BI prefetch units; 
 prefetch the non-BIs addressed by the non-BPCs by accessing the initial locations of the NIs in the non-BIs; 
 prefetch the other NIs consecutively located in the same non-BIs until the termination value of the last NIs of the non-BIs are prefetched; 
 prefetch variable-length NIs by the NPC values stored in the NPCs in the non-BI prefetch units; 
 update the NPC values stored in the non-BPCs for prefetching the next non-BIs; 
 fetch the non-BIs from the locations addressed by the program counters in the non-BI fetch units whenever the associated BIs are fetched by the BI fetch units; 
 fetch the non-BIs addressed by the non-BPCs by accessing the initial locations of the NIs in the non-BIs; 
 fetch the other NIs consecutively located in the same non-BIs until the termination values of the last NIs of the single or plurality of non-BIs is fetched; 
 fetch variable-length NIs by the NPC values stored in the NPCs in the non-BI prefetch units; 
 update the single or plurality of NPC values stored in the non-BPCs for fetching the next non-BIs; 
 fetch non-BIs before decoding a single or plurality of non-BIs and/or NIs; 
 transmit the decode results of the fetched non-BIs and/or NIs to the backend processing engines in the backend microprocessors; 
 store the BIs fetched from the BI/non-BI memory systems via the BI/non-BI prefetch/fetch systems in the BIQs in the BI fetch units; 
 update the next BI addresses to the BPCs in the BI fetch units if the current BIs do not represent any branch instructions fetched; 
 update the BPCs with a single or plurality of addresses of the BIs at the branch target locations if the current BIs represent the branch instructions fetched; 
 fetch BIs from the BIQs to the BI decode units if the BIQs are used; 
 decode the fetched BIs from the BIQs or directly forwarded from the BI fetch units at the BI decode units; 
 decode the BIs to redirect the associated non-BIs fetched to the non-BIQs in the non-BI fetch units if the fetched non-BIs in the non-BIQs are changed at the BI decode units; 
 screen any BIs required to be predicted their branch operations and branch target locations by the BI decode units; 
 forward the information for branch prediction to the BLA branch prediction units; 
 initiate the branch prediction of the BIs received from the BI decode units within a single or plurality of clock cycles ahead comparing with the branch prediction with the NIs fetched and decoded in the non-BI fetch units and the non-BI decode units; 
 initiate the next BI and non-BI prefetch and fetch operations with the branch prediction results available a single or plurality of clock cycles ahead for reducing taken-branch latencies and consequently enhancing performance of the microprocessors; 
 filter a BI representing a loop by the BI decode units and hold further BI fetch operations in the BI fetch units while reissuing the same BIs representing the same loop to the BAL branch prediction units; 
 eliminate recursive BI and non-BI prefetching and fetching operations from the BI/non-BI memory systems to the BRA systems via the BI/non-BI prefetch/fetch systems; 
 detect and process the disrupted BI and non-BI fetch, decode, and/or execution orders; 
 push the current BPCs, non-BPCs, and/or NPCs to the stacks in order to resume the disrupted BI, non-BI, and/or NI operations; 
 update new NPC values to the BPCs, non-BPCs, and/or NPCs; 
 prefetch and fetch the BI, non-BI, and/or NIs from the disrupted locations in the program; 
 retrieve the values of the BPCs, non-BPCs, and/or NPCs stored in the stacks to the BPCs, non-BPCs and/or NPCs after the disrupted operations are completed; 
 reset a single or plurality of values of the non-BPCs and/or values of NPCs whenever the last NIs of the associated non-BIs are fetched; 
 increase the values of the non-BPCs and/or NPCs whenever non-BIs and/or NIs of the next non-BIs are fetched; 
 reset the values of the non-BPCs and/or NPCs whenever the first NIs of the associated non-BIs are fetched; 
 increase the values of the non-BPCs and/or the values of NPCs whenever non-BIs and/or NIs of the same non-BIs are fetched; and 
 continue for updating the non-BPCs and/or NPCs until the next non-BIs and/or the last NIs of the non-BIs are fetched. 
   
     
     
         4 . The dynamic BI/non-BI assembling and delivering systems of  claim 3 , wherein the single or plurality of BI/non-BI memory systems further comprises:
 a single or plurality of BI memories;   a single or plurality of levels of BI caches;   a single or plurality of non-BI memories; and   a single or plurality of levels of non-BI caches; wherein the BI/non-BI memory system is operable to:
 allocate the BIs in the BI program and non-BIs in the non-BI program to the different locations of the sequentially, concurrently, and/or a plurality of times quickly accessible caches and main memories separately; 
 access the same or different sizes of the same or different number of banks from the levels of the caches in the sequentially, concurrently, and/or a plurality of times quickly accessible BI and non-BI caches and main memories if necessary; 
 prefetch non-BIs concurrently by allocating the NIs of the consecutive BIs to the different banks in the sequentially, concurrently, and/or a plurality of times quickly accessible non-BI caches and main memories; 
 store the non-BI located right after a branch instruction in the program to the different bank where the non-BIs are located at the branch target locations of the branch instructions for the concurrent prefetch and/or fetch; 
 store the non-BIs to the different banks of the non-BI main memories in the circular manner for reassembling the NIs from the associated non-BIs; 
 store the BIs to the different locations of the sequentially, concurrently, and/or a plurality of times quickly accessible BI main memories; 
 access the same or different sizes of the same or different number of banks from a single or plurality of the sequentially, concurrently, and/or a plurality of times quickly accessible BI main memories during the BI assembling and delivering time; 
 store a single or plurality of BIs to the same or different sizes of the same or different number of banks in the levels of the caches in the sequentially, concurrently, and/or a plurality of times quickly accessible BI caches during the BI assembling and delivering time; 
 store the BIs to the different locations of the sequentially, concurrently, and/or a plurality of times quickly accessible the levels of BI caches; 
 access the same or different sizes of the same or different number of banks from a single or plurality of the sequentially, concurrently, and/or a plurality of times quickly accessible BI caches; 
 store a single or plurality of BIs to a single or plurality of BI prefetch and decode units, a single or plurality of BI fetch and decode units, and/or a single or plurality of BLA systems; 
 store the non-BIs and/or NIs in the non-BI program to the different locations of the sequentially, concurrently, and/or a plurality of times quickly accessible non-BI main memories; 
 access the same or different sizes of the same or different number of banks from a single or plurality of the sequentially, concurrently, and/or a plurality of times quickly accessible non-BI main memories during the non-BI assembling and delivering time; 
 store a single or plurality of non-BIs to the same or different sizes of the same or different number of banks in a single or plurality of levels of the caches in the sequentially, concurrently, and/or a plurality of times quickly accessible non-BI caches; 
 store the non-BI and/or NIs to the different locations of the sequentially, concurrently, and/or a plurality of times quickly accessible a single or plurality of levels of non-BI caches; 
 access the same or different sizes of the same or different number of banks from a single or plurality of the sequentially, concurrently, and/or a plurality of times quickly accessible non-BI caches during the non-BI assembling and delivering time; and 
 store a single or plurality of non-BIs and/or NIs to a single or plurality of non-BI prefetch units, a single or plurality of non-BI fetch units, and/or a single or plurality of BLA systems. 
   
     
     
         5 . The dynamic BI/non-BI assembling and delivering systems of  claim 3 , wherein the single or plurality of BI/non-BI prefetch/fetch systems further comprises:
 a single or plurality of BI prefetch and decode units;   a single or plurality of prefetch BPCs;   a single or plurality of BI fetch and decode units;   a single or plurality of fetch BPCs;   a single or plurality of non-BI prefetch units;   a single or plurality of prefetch non-BPCs;   a single or plurality of non-BI fetch units; and   a single or plurality of fetch non-BPCs; wherein the apparatus for producing the single or plurality of BI/non-BI prefetch/fetch systems is operable to:
 assemble the non-BIs stored in the non-BI main memories via the non-BI caches according to the associated BIs stored in the BI main memories and caches after delivering BIs to the BI/non-BI prefetch/fetch systems during the BI/non-BI assembling and delivering time; 
 prefetch the BIs from the locations addressed by the program counters in a single or plurality of BI prefetch/decode units whenever the associated BPCs in the BI prefetch/decode units are updated with new NPC values by decoding the prefetched BIs with the BI prefetch/decode units or by receiving the NPC values from the BLA systems; 
 receive the new NPC values for prefetching BIs from the BLA systems whenever a single or plurality of branch target addresses is obtained via the BLA branch prediction units in the BLA systems or the interrupt processing units in the backed microprocessors; 
 terminate current BI prefetch operations after prefetching BIs in two different paths for the precise BI prefetch, when the conditional BIs in the program representing any conditional branch instructions requiring branch prediction are detected; 
 decode the prefetched BIs to provide new non-BPC values for prefetching the associated non-BIs to the non-BI prefetch units and non-BPCs and/or to provide the NPC values stored in the NPCs in the non-BI prefetch units for prefetching variable-length NIs; 
 fetch the BIs from the locations addressed by the program counters in the BI fetch/decode units whenever the associated BPCs in the BI fetch/decode units are updated with new NPC values by decoding the fetched BIs with the BI fetch/decode units or by receiving the NPC values from the BLA systems; 
 receive the new NPC values for fetching BIs from the BLA systems whenever a branch target address is obtained via the BLA branch prediction units in the BLA systems or the interrupt processing units in the backed microprocessors; 
 decode the fetched BIs to provide a new non-BPC values for fetching the associated non-BIs to the non-BI fetch units and non-BPCs and/or to provide the NPC values stored in the NPCs in the non-BI fetch units for fetching variable-length NIs; 
 store the fetched BIs in BIQs or forward to the BI decode units via the BI fetch units; 
 screen any BIs required to be predicted their branch operations and branch target locations; 
 forward the information for branch prediction to the BLA branch prediction units; 
 initiate the branch prediction operations of the BIs received within a single or plurality of clock cycles ahead comparing with the branch prediction operations with NIs fetched and decoded in the non-BI fetch units and the non-BI decode units; 
 initiate next BI and non-BI prefetch and fetch operations according to the branch prediction results available a single or plurality of clock cycles ahead for enhancing performance of the microprocessor by reducing taken-branch latencies; 
 filter BIs representing a single or plurality of loops by the BI decode units and hold further BIs fetched in the BI fetch units while reissuing the same BIs representing the same single or plurality of loops to the BAL branch prediction units; and 
 eliminate recursive BI and non-BI prefetching and fetching operations from the BI/non-BI memory systems to the BRA systems via the BI/non-BI prefetch/fetch systems. 
   
     
     
         6 . The BI/non-BI prefetch/fetch systems of  claim 5 , wherein the single or plurality of BI prefetch and decode/fetch units is operable to:
 prefetch the BIs addressed by the associated BPCs via the BI/non-BI memory systems;   prefetch the BI representing a native branch target instruction from one path and the BI located at the next location in the BI program from another path;   prefetch continuously a BI representing a native unconditional branch instruction providing their branch target address from the branch target location of the BI;   discard unconditional BIs after obtaining its branch target locations in order not to fetch the unconditional BIs to the backend microprocessors via the BLA systems;   obtain branch target addresses from various branch predictors and branch target buffers can be used if necessary;   terminate a precise BI prefetch after prefetching BIs in two different paths, when the conditional BIs representing any conditional branch instructions requiring branch prediction are detected;   decode the prefetched BIs to prefetch the associated non-BIs;   provide a single or plurality of addresses for sequentially and/or concurrently prefetching the BIs from the BI memories via the levels of BI caches;   receive a single or plurality of NPC values from the BLA systems for resuming a single or plurality of BI prefetch operations.   fetch sequentially and/or concurrently the BIs addressed by the associated BPCs from the BI memories via the levels of BI caches;   fetch the BIs from the locations addressed by the BPCs in the BI fetch/decode units whenever the associated BPCs in the BI fetch/decode units are updated with new NPC values by decoding the fetched BIs with the BI fetch/decode units;   fetch the BIs from the locations received by the NPC values from the BLA systems whenever a branch target address is obtained via the BLA branch prediction units in the BLA systems;   fetch the BIs from the locations addressed by the interrupt processing units in the backed microprocessors;   fetch variable-length NIs from the NPC values stored in the NPCs in the non-BI fetch units;   provide a single or plurality of addresses for sequentially and/or concurrently fetching the BIs from the BI memories via the levels of BI caches;   receive a single or plurality of NPC values from the BLA systems for resuming a single or plurality of BI fetch operations;   
     
     
         7 . The BI/non-BI prefetch/fetch systems of  claim 5 , wherein the single or plurality of non-BI prefetch/fetch units is operable to:
 prefetch the non-BIs from the locations addressed by the program counters in the non-BI prefetch units whenever the associated BIs are prefetched by the BI prefetch/decode units;   prefetch the non-BIs addressed by the non-BPCs by accessing the initial locations of the NIs in the non-BIs;   prefetch the other NIs consecutively located in the same non-BIs until the termination values of the last NIs of the non-BIs are prefetched;   prefetch variable-length NIs by the NPC values stored in the NPCs in the non-BI prefetch units;   update the single or plurality of NPC values stored in the non-BPCs for prefetching the next non-BIs;   provide a single or plurality of addresses for sequentially and/or concurrently prefetching the non-BI and/or NIs from the non-BI memories via the levels of non-BI caches;   receive a single or plurality of NPC values from the BLA systems for resuming a single or plurality of non-BAL and/or NI prefetch operations;   fetch sequentially and/or concurrently the non-BI and/or NIs addressed by the associated non-BPCs from the non-BI memories via the levels of non-BI caches;   fetch the non-BI and/or NIs from the locations addressed by the program counters in the non-BI fetch units whenever the associated non-BPCs in the non-BI fetch units are updated with new NPC values by decoding the fetched BIs with the BI fetch/decode units;   fetch the non-BI and/or NIs from the locations received by the NPC values from the BLA systems whenever a branch target address is obtained via the BLA branch prediction units in the BLA systems;   fetch the non-BI and/or NIs from the locations addressed by the interrupt processing units in the backed microprocessors;   fetch the non-BI and/or NIs from the locations addressed by the backend processing engines in the microprocessors for correcting mispredicted branches;   fetch variable-length NIs from the NPC values stored in the NPCs in the non-BI fetch units;   provide a single or plurality of addresses for sequentially and/or concurrently fetching the non-BI and/or NIs from the non-BI memories via the levels of non-BI caches; and   receive a single or plurality of NPC values from the BLA systems for resuming a single or plurality of non-BI and/or NI fetch operations.   
     
     
         8 . The dynamic BI/non-BI assembling and delivering systems of  claim 3 , wherein the single or plurality of BLA systems further comprises:
 a single or plurality of BI fetch units;   a single or plurality of BI decode units;   a single or plurality of BIQs;   a single or plurality of BPCs;   a single or plurality of BLA branch prediction units;   a single or plurality of non-BI fetch units;   a single or plurality of non-BI decode units;   a single or plurality of non-BIQs;   a single or plurality of non-BPCs;   a single or plurality of NIQs for NIs; and   a single or plurality of NPCs for NIs;   wherein the apparatus for producing the single or plurality of BLA systems is operable to:
 store the fetched BIs to BIQs or forward to the BI decode units via the BI fetch units; 
 screen any BIs required to be predicted their branch operations and branch target locations; 
 forward the information for branch prediction to the BLA branch prediction units; 
 initiate the branch prediction operations of the BIs received within a single or plurality of clock cycles ahead comparing with the branch prediction operations with NIs fetched and decoded in the non-BI fetch units and the non-BI decode units; 
 initiate next BI and non-BI prefetch and fetch operations according to the branch prediction results available a plurality of clock cycles ahead for enhancing performance of the microprocessor by reducing taken-branch latencies; 
 filter BIs representing a single or plurality of loops by the BI decode units and hold further BIs fetched in the BI fetch units while reissuing the same BIs representing the same single or plurality of loops to the BAL branch prediction units; 
 eliminate recursive BI and non-BI prefetching and fetching operations from the BI/non-BI memory systems to the BRA systems via the BI/non-BI prefetch/fetch systems; 
 decode the BIs to redirect the associated non-BI and/or NIs fetched to the non-BIQs in the non-BI fetch units if the fetched non-BIs and/or NIs in the non-BIQs are changed; 
 detect and process the disrupted operations of BI, non-BI, and/or NI fetch, decode, and execution orders, such as interrupts, by the interrupt processing units; 
 store the current BPCs, non-BPCs, and/or NPCs to the stack in order to resume the disrupted operations of the BIs, non-BIs, and/or NIs; 
 update new NPC values to the BPCs in the BI fetch units and/or non-BPCs and/or NPCs in the non-BI fetch units to prefetch and/or fetch the BIs, non-BIs, and/or NIs from the disrupted locations; 
 restore values of the BPCs, non-BPCs, and/or NPCs stored in the stack to the BPC and/or non-BPC and/or NPC; 
 reset values of the non-BPCs and/or values of NPCs whenever the last NIs of the associated non-BIs are fetched; 
 increase the values of the non-BPCs and/or NPCs whenever a non-BI and/or a NI of the next non-BI are fetched or whenever the first NIs of the associated non-BIs are fetched; 
 repeat resetting and increasing the values of the non-BPCs and/or NPCs until the next non-BIs and/or the last NIs of the non-BIs are fetched; 
 transmit the new NPC values for prefetching BIs to the BI memories and/or caches whenever a single or plurality of branch target addresses is obtained via the BLA branch prediction units in the BLA systems or the interrupt processing units in the backed microprocessors; and 
 transmit the new NPC values for fetching BIs to the BI memories and/or caches whenever a single or plurality of branch target addresses is obtained via the BLA branch prediction units in the BLA systems or the interrupt processing units in the backed microprocessors. 
   
     
     
         9 . The BLA systems of  claim 8 , wherein the single or plurality of BI fetch units is operable to:
 fetch a single or plurality of BIs from the locations received by the BPCs from the BI caches and/or memories via the BI prefetch and fetch systems;   fetch BIs from the BIQs to the BI decode units if the BIQs are used;   store the fetched BIs to a single or plurality of entries of the BIQs by the same BI fetch order if the BIQs are used;   forward the fetched BIs in the BIQs to the BI decode units in the BLA systems if the BIQs are used;   adjust access pointers of the BIQs for writing next fetched BIs to and reading next decoded BIs from the BIQs;   update the next BI addresses to the BPCs in the BI fetch units if the current BIs do not represent any branch instructions fetched;   update the BPCs with a single or plurality of addresses of the BIs at the branch target locations if the current BIs represent the branch instructions fetched;   receive the branch prediction results available a single or plurality of clock cycles ahead from the BLA branch prediction units;   receive a single or plurality of NPC values of BPCs for performing the disrupted operations of the BI fetch and/or decode orders, such as interrupts by the interrupt processing units, branch misprediction corrections by the backend processing engines, and other disrupted operations occurred in microprocessors;   update new NPC values to the BPCs to prefetch and/or fetch the BIs from the disrupted locations;   restore NPC values of the BPC stored in the stack to the BPCs;   forward again the same fetched BIs representing a single or plurality of loops in BIQs to the BI decode units according to the branch prediction results received; and   hold the BI fetch operations for fetching any BIs from the BI prefetch/fetch systems whenever forwarding the same fetched BIs representing a single or plurality of loops in BIQs to the BI decode units.   
     
     
         10 . The BLA systems of  claim 8 , wherein the single or plurality of BI decode units is operable to:
 receive a single or plurality of fetched BIs from the BI fetch units in the BLA systems;   decode the fetched BIs to provide new non-BPC values for fetching the associated non-BIs to the non-BI fetch units and non-BPCs and/or to provide the NPC values stored in the NPCs in the non-BI fetch units for fetching fixed- and variable-length NIs;   screen any BIs required to be predicted their branch operations and branch target locations;   forward the information for branch prediction to the BLA branch prediction units;   filter BIs representing a single or plurality of loops while forwarding the same BIs representing the same single or plurality of loops to the BAL branch prediction units;   decode the BIs to redirect the associated non-BIs fetched to the non-BIQs in the non-BI fetch units if the fetched non-BIs and/or NIs in the non-BIQs are changed;   transmit the decoded information of the BIs to fetch the associated non-BIs and/or NIs from the non-BI prefetch/fetch systems to the non-BI fetch units or to the non-BIQs in the non-BI fetch units if the non-BIQs are used;   fetch a single or plurality of BIs fetched sequentially or concurrently from the BI memories and caches via the BI prefetch/fetch systems;   store the fetched BIs sequentially or concurrently through a single or plurality of entries of the BIQs;   dispatch the fetched BIs sequentially or concurrently from a single or plurality of entries of the BIQs to the BI decode units;   fetch and dispatch a non-scaled BI representing the non-BI disassembled or a segment of the entire NIs, such as all NIs in a basic block, sequentially;   fetch and dispatch a scaled BI representing a single or plurality of non-BIs disassembled or a single or plurality of sub-segments of the NI segment, such as some NI sub-segments in a basic block, concurrently;   hole a single or plurality of current BI addresses to fetch the BIs from the BI caches and/or memories via the BI prefetch and fetch systems to the BI fetch units in the BLA systems;   update the single or plurality of next BI addresses if the current BIs do not represent any branch instructions fetched;   update the single or plurality of addresses of the BIs at the branch target locations if the current BIs represent the branch instructions fetched;   update values of the single or plurality of current or next BPCs to the stacks in order to resume the disrupted BI operations; and   retrieve the NPC values stored in the stacks to the BPCs after the disrupted operations are completed.   
     
     
         11 . The BLA systems of  claim 8 , wherein the single or plurality of BLA branch prediction units is operable to:
 receive the information for branch prediction from the BI decode units;   access other information for branch prediction from a single or plurality of other useful units found in prior arts including branch predictor and history table;   produce the new NPC values for prefetching and fetching BIs from the BLA systems whenever a single or plurality of branch target addresses is obtained via the BLA branch prediction units in the BLA systems;   transmit the new NPC values for prefetching and fetching BIs to the BI fetch units whenever a single or plurality of branch target addresses is produced; and   update the necessary information for branch prediction to the associated sub-units including branch predictor and history table.   
     
     
         12 . The BLA systems of  claim 8 , wherein the single or plurality of non-BI fetch/decode units is operable to:
 fetch sequentially and/or concurrently the non-BIs and/or NIs addressed by the associated non-BPCs and/or NPCs from the non-BI memories via the levels of non-BI caches;   fetch the non-BIs and/or NIs from the locations addressed by the program counters in the non-BI fetch units whenever the associated non-BPCs and/or NPCs in the non-BI fetch units are updated with new NPC values by decoding the fetched BIs with the BI fetch units;   fetch the non-BIs and/or NIs from the locations received by the NPC values from the branch prediction units whenever a single or plurality of branch target addresses is obtained via the BLA branch prediction units;   fetch the non-BIs and/or NIs from the locations addressed by the interrupt processing units in the backed microprocessors;   fetch the non-BIs and/or NIs from the locations addressed by the backend processing engines in the backed microprocessors for correcting mispredicted branches;   fetch variable-length NIs from the NPC values stored in the NPCs in the non-BI fetch units;   fetch non-BIs and/or NIs from the non-BIQs and/or NIQs to the non-BI decode units if the non-BIQs are used;   store the fetched non-BIs and/or NIs to a single or plurality of entries of the non-BIQs and/or NIQs in the same non-BI and/or NI fetch order if the BIQs are used;   store the fetched NIs to a single or plurality of entries of the NIQs in the same NI fetch order if the BIQs are not used;   forward the fetched non-BIs and/or NIs in the non-BIQs and/or NIQs to the non-BI decode units in the BLA systems if the BIQs are used;   adjust access pointers of the non-BIQs and/or NIQs for writing next fetched non-BIs and/or NIs to and reading next decoded non-BIs and/or NIs from the non-BIQs and/or NIQs;   update the next non-BI and/or NI addresses to the non-BPCs and/or NPCs in the non-BI fetch units if the current non-BIs and/or NIs do not represent any branch instructions fetched;   update the non-BPCs and/or NPCs with a single or plurality of addresses of the non-BIs and/or NIs at the branch target locations if the current non-BIs and/or NIs represent the branch instructions fetched;   receive the branch prediction results available to a single or plurality of clock cycles ahead from the BLA branch prediction units;   receive a single or plurality of NPC values of non-BPCs and/or NPCs for performing the disrupted operations of the non-BI and/or NI fetch and/or decode orders, such as interrupts by the interrupt processing units, branch misprediction corrections by the backend processing engines, and other disrupted operations occurred in microprocessors;   update new NPC values to the non-BPCs and/or NPCs to prefetch and/or fetch the non-BIs and/or NIs from the disrupted locations;   restore NPC values of the non-BPCs and/or NPCs stored in the stack to the non-BPCs and/or NPCs;   forward again the same fetched non-BI and/or NIs representing a single or plurality of loops in the non-BIQs and/or NIQs to the decode units according to the branch prediction results received;   hold the non-BI and/or NI fetch operations for fetching any non-BIs and/or NIs from the non-BI prefetch/fetch systems whenever forwarding the same fetched non-BIs and/or NIs representing a single or plurality of loops in the non-BIQs and/or NIQs to the non-BI decode units;   receive a single or plurality of fetched non-BIs and/or NIs from the non-BI fetch units in the BLA systems;   decode the fetched non-BIs and/or native conditional branch instructions to provide new values of the non-BPCs and/or NPCs for fetching the non-BI and/or fixed- and variable-length NIs to the non-BI fetch units;   screen any non-BIs and/or NIs required to be predicted their branch operations and branch target locations if any BIs are not fetched;   forward the information for branch prediction to the non-BI and/or native branch prediction units if any BIs are not fetched;   filter non-BIs and/or NIs representing a single or plurality of loops while forwarding the same non-BIs and/or NIs representing the same single or plurality of loops to the non-BI and/or native branch prediction units if any BIs are not fetched;   transmit the decoded information of the non-BIs and/or NIs to fetch the associated non-BIs and/or NIs from the non-BI prefetch/fetch systems to the non-BI fetch units if any BIs are not fetched or to the non-BIQs in the non-BI fetch units if the non-BIQs are used and any BIs are not fetched;   fetch a single or plurality of non-BIs and/or NIs fetched sequentially or concurrently from the non-BI memories and caches via the non-BI prefetch/fetch systems;   store the fetched non-BIs and/or NIs sequentially or concurrently through a single or plurality of entries of the non-BIQs and/or NIQs;   dispatch the fetched non-BIs and/or NIs sequentially or concurrently from a single or plurality of entries of the non-BIQs and/or NIQs to the non-BI decode units;   fetch and dispatch a single or plurality of non-scaled non-BIs and/or NIs sequentially;   fetch and dispatch a single or plurality of scaled non-BIs and/or NIs concurrently;   hole a single or plurality of current non-BI and/or NI addresses to fetch the non-BIs and/or NIs from the non-BI caches and/or memories via the non-BI prefetch and fetch systems to the non-BI fetch units in the BLA systems;   update the single or plurality of next non-BI and/or NI addresses if the current non-BIs and/or NIs do not represent any branch instructions fetched;   update the single or plurality of addresses of the non-BIs and/or NIs at the branch target locations if the current non-BIs and/or NIs represent the branch instructions fetched;   update a single or plurality of current or next non-BPCs' and/or NPCs' values to the stacks in order to resume the disrupted non-BI and/or NI operations;   retrieve the NPC values stored in the stacks to the non-BPCs and/or NPCs after the disrupted operations are completed;   fetch a single or plurality of NIs fetched sequentially or concurrently from the non-BI memories and caches via the non-BI prefetch/fetch systems if any BIs are not fetched;   store the fetched NIs sequentially or concurrently through a single or plurality of entries of the NIQs if any BIs are not fetched;   dispatch the fetched a single or plurality of NIs sequentially or concurrently from a single or plurality of entries of the NIQs to the non-BI decode units if any BIs are not fetched;   fetch and dispatch a single or plurality of NIs sequentially if any BIs are not fetched;   hole a single or plurality of current NI addresses to fetch the NIs from the non-BI caches and/or memories via the non-BI prefetch and fetch systems to the non-BI fetch units in the BLA systems if any BIs are not fetched;   update the single or plurality of next NI addresses if the current NIs do not represent any branch instructions fetched if any BIs are not fetched;   update the single or plurality of addresses of the NIs at the branch target locations if the current NIs represent the branch instructions fetched if any BIs are not fetched;   update a single or plurality of current or next NPCs' values to the stacks in order to resume the disrupted NI operations if any BIs are not fetched; and   retrieve the NPC values stored in the stacks to the NPCs after the disrupted operations are completed if any BIs are not fetched.   
     
     
         13 . The apparatus for producing a BI disassembling, assembling, and delivering system of  claim 1 , wherein the single or plurality of backend microprocessors is comprising:
 a single or plurality of interrupt processing units;   a single or plurality of stacks; and   a single or plurality of backend processing engines; wherein the apparatus for producing the single or plurality of backend microprocessors is operable to:
 receive the decode results of the fetched non-BIs and/or NIs from the non-BI decode units to the backend processing engines in the backend microprocessors; 
 initiate a single or plurality of disrupted operations, such as interrupts, branch misprediction corrections and other disrupted operations occurred in microprocessors; 
 receive values of the BPCs, non-BPCs, and/or NPCs to store the values to the stack memory for resuming the currently disrupted BI, non-BI, and/or NI operations; 
 transmit a single or plurality of the values of BPCs, non-BPCs, and/or NPCs for performing the disrupted operations of the BI, non-BI, and/or NI fetch and/or decode orders, such as interrupts by the interrupt processing units, branch misprediction corrections by the backend processing engines, and other disrupted operations occurred in microprocessors; 
 transmit the values of the BPCs, non-BPCs, and/or NPCs stored in stack memory to the BPCs, non-BPCs, and/or NPCs for resuming the disrupted BI, non-BI, and/or NI operations after completing the currently disrupted operations; 
 receive a single or plurality of interrupt requests; 
 initiate a single or plurality of disrupted operations, such as interrupts; 
 receive the values of the BPCs, non-BPCs, and/or NPCs; 
 store the BPCs, non-BPCs, and/or NPCs to the stack memory for resuming the currently disrupted BI, non-BI, and/or NI operations; 
 transmit a single or plurality of values of the BPCs, non-BPCs, and/or NPCs for performing the interrupt operations of the BI, non-BI, and/or NI fetch and/or decode orders; 
 transmit the values of the BPCs, non-BPCs, and/or NPCs stored in stack memory to the BPCs, non-BPCs, and/or NPCs for resuming the disrupted BI, non-BI, and/or NI operations after completing the currently disrupted operations; 
 initiate a single or plurality of disrupted operations, such as branch misprediction corrections and other disrupted operations occurred; 
 store the values of the BPCs, non-BPCs, and/or NPCs for resuming the currently disrupted BI, non-BI, and/or NI operations; 
 transmit the values of the BPCs, non-BPCs, and/or NPCs stored to the BPCs, non-BPCs, and/or NPCs for resuming the disrupted BI, non-BI, and/or NI operations after completing the currently disrupted operations; 
 receive the decode results of the fetched non-BIs and/or NIs from the non-BI decode units; 
 initiate a single or plurality of disrupted operations, such as branch misprediction corrections and other disrupted operations occurred; 
 receive the values of the BPCs, non-BPCs, and/or NPCs to store them to the stack memory for resuming the currently disrupted BI, non-BI, and/or NI operations; 
 transmit a single or plurality of values of the BPCs, non-BPCs, and/or NPCs for performing the disrupted operations of the BI, non-BI, and/or NI fetch and/or decode orders, such as branch misprediction corrections by the backend processing engines, and other disrupted operations occurred in microprocessors; and 
 transmit the values of the BPCs, non-BPCs, and/or NPCs stored in stack memory to the BPCs, non-BPCs, and/or NPCs for resuming the disrupted BI, non-BI, and/or NI operations after completing the currently disrupted operations. 
   
     
     
         14 . A method comprising:
 disassembling, by a BI and non-BI disassembling system, the NIs in a software and/or assembly program to BI program and non-BI program;   eliminating, by the BI and non-BI disassembling system, native branch instructions used in the software and/or assembly program;   composing, by the BI and non-BI disassembling system, BIs in the BI program comprising another BIs and non-disassembled NIs;   composing, by the BI and non-BI disassembling system, a single or plurality of BIs representing a single or plurality of levels of loops in the software and/or assembly program;   composing, by the BI and non-BI disassembling system, non-BIs in the non-BI program comprising another non-BIs and non-disassembled NIs;   composing, by the BI and non-BI disassembling system, a single or plurality of non-BIs representing a single or plurality of levels of loops in the software and/or assembly program;   allocating, by the dynamic BI/non-BI assembling and delivering systems, BI and non-BIs to the different locations of the sequentially, concurrently, and/or a plurality of times quickly accessible caches and main memories;   assembling, by the dynamic BI/non-BI assembling and delivering systems, the non-BI program stored in the non-BI memories via the non-BI caches according to the associated BI program stored in the BI memories and caches;   delivering, by the dynamic BI/non-BI assembling and delivering systems, BIs to the BI/non-BI prefetch/fetch systems;   obtaining, by the dynamic BI/non-BI assembling and delivering systems, a single or plurality of branch target addresses via the BLA branch prediction units in the BLA systems or the interrupt processing units in the backed microprocessors;   receiving, by the dynamic BI/non-BI assembling and delivering systems, the new NPC values for prefetching BIs from the BLA systems;   updating, by the BI and non-BI prefetch and fetch systems, the associated BPCs in the BI prefetch/decode units with new NPC values obtained by decoding the prefetched BIs with the BI prefetch/decode units or by receiving the NPC values from the BLA systems;   prefetching, by the BI and non-BI prefetch and fetch systems, the BIs from the locations addressed by the program counters in the BI prefetch/decode units;   prefetching, by the BI and non-BI prefetch and fetch systems, BIs in two different paths for the precise BIs prefetching, when the conditional BI representing any native conditional branch instructions requiring branch prediction is detected;   terminating, by the BI and non-BI prefetch and fetch systems, current BI prefetching operations after prefetching the BIs in two different paths;   decoding, by the BI and non-BI prefetch and fetch systems, the prefetched BIs to provide new non-BPC values for prefetching the associated non-BIs to the non-BI prefetch units and non-BPCs and/or to provide a single or plurality of values stored in the NPCs in the non-BI prefetch units for prefetching variable-length NIs;   fetching, by the BI and non-BI prefetch and fetch systems, the BIs from the locations addressed by the program counters in the BI fetch/decode units whenever the associated BPCs in the BI fetch/decode units is updated with new NPC values by decoding the fetched BIs with the BI fetch/decode units or by receiving the NPC values from the BLA systems;   receiving, by the BI and non-BI prefetch and fetch systems, the new NPC values for fetching BIs from the BLA systems whenever a branch target address is obtained via the BLA branch prediction units in the BLA systems or the interrupt processing units in the backed microprocessors;   decoding, by the BI and non-BI prefetch and fetch systems, the fetched BIs to provide new non-BPC values for fetching the associated non-BIs to the non-BI fetch units and non-BPCs and/or to provide the values stored in the NPCs in the non-BI fetch units for fetching variable-length NIs;   storing, by the BLA systems, the fetched BIs in the BIQs or forwarding to the BI decode units via the BI fetch units;   screening, by the BI decode units, any BIs required to be predicted their branch operations and branch target locations;   forwarding, by the BI decode units, the information for branch prediction to the BLA branch prediction units;   initiating, by the BLA branch prediction units, the branch prediction operations of the BIs received within a single or plurality of clock cycles ahead comparing with the branch prediction operations with NIs fetched and decoded in the non-BI fetch units and the non-BI decode units;   initiating, by the BLA systems, next BI and non-BI prefetch and fetch operations according to the branch prediction results available to a single or plurality of clock cycles ahead for enhancing performance of the microprocessor by reducing taken-branch latencies;   filtering, by the BI decode units, BIs representing a single or plurality of loops;   holding, by the BI decode units, further BIs fetched in the BI fetch units;   reissuing, by the BI decode units, the same BIs representing the same single or plurality of loops to the BAL branch prediction units;   eliminating, by the BLA systems, recursive BI and non-BI prefetching and fetching operations from the BI/non-BI memory systems to the BRA systems via the BI/non-BI prefetch/fetch systems;   decoding, by the BI decode units, the BIs to redirect the associated non-BIs fetched to the non-BIQs in the non-BI fetch units if the fetched non-BIs and/or NIs in the non-BIQs are changed;   detecting and processing, by the BLA systems, the disrupting operations of the BI, non-BI, and/or NI fetch, decode, and/or execution orders, such as interrupts by the interrupt processing units, branch misprediction correction operations by the backend processing engines, and other parts in microprocessors;   storing, by the interrupt processing units or by the BLA systems, current BPCs, non-BPCs, and/or NPCs to the stacks in order to resume the disrupted operations of the BI, non-BI, and/or NIs;   updating, by the BLA systems, new NPC values to the BPCs in the BI fetch units and/or non-BPCs and/or NPCs in the non-BI fetch units to prefetch and/or fetch the BI, non-BI, and/or NIs from the disrupted locations;   restoring, by the BLA systems, NPC values of the BPCs, non-BPCs, and/or NPCs stored in the stacks to the BPCs and/or non-BPCs and/or NPCs;   resetting, by the non-BI fetch units, a single or plurality of values of the non-BPCs and/or NPCs whenever the last NIs of the associated non-BIs are fetched;   increasing, by the non-BI fetch units, a single or plurality of values of the non-BPCs and/or NPCs whenever non-BIs and/or NIs of the next non-BIs are fetched or whenever the first NIs of the associated non-BIs are fetched; and   repeating, by the non-BI fetch units, resetting and increasing the values of the non-BPCs and/or NPCs until the next non-BIs and/or the last NIs of the non-BIs are fetched;   
     
     
         15 . The method of  claim 14 , wherein the single or plurality of BLA systems further comprises:
 a single or plurality of BI fetch units;   a single or plurality of BIQs;   a single or plurality of BPCs;   a single or plurality of BI decode units;   a single or plurality of BLA branch prediction units;   a single or plurality of non-BI fetch units;   a single or plurality of non-BIQs;   a single or plurality of non-BPCs;   a single or plurality of NIQs for NIs;   a single or plurality of NPCs for NIs; and   a single or plurality of non-BI decode units; wherein the single or plurality of BLA systems is operable to:
 store the fetched BIs to BIQs or forward to the BI decode units via the BI fetch units; 
 screen any BIs required to be predicted their branch operations and branch target locations; 
 forward the information for branch prediction to the BLA branch prediction units; 
 initiate the branch prediction operations of the BIs received within a single or plurality of clock cycles ahead comparing with the branch prediction operations with NIs fetched and decoded in the non-BI fetch units and the non-BI decode units; 
 initiate next BI and non-BI prefetch and fetch operations according to the branch prediction results available a plurality of clock cycles ahead for enhancing performance of the microprocessor by reducing taken-branch latencies; 
 filter BIs representing a single or plurality of loops by the BI decode units and hold further BIs fetched in the BI fetch units while reissuing the same BIs representing the same single or plurality of loops to the BAL branch prediction units; 
 eliminate recursive BI and non-BI prefetching and fetching operations from the BI/non-BI memory systems to the BRA systems via the BI/non-BI prefetch/fetch systems; 
 decode the BIs to redirect the associated non-BIs and/or NIs fetched to the non-BIQs in the non-BI fetch units if the fetched non-BIs and/or NIs in the non-BIQs are changed; 
 detect and process the disrupted operations of BI, non-BI, and/or NI fetch, decode, and execution orders, such as interrupts, by the interrupt processing units; 
 store the current BPCs, non-BPCs, and/or NPCs to the stack in order to resume the disrupted operations of the BI, non-BI, and/or NIs; 
 update new NPC values to the BPCs in the BI fetch units and/or non-BPCs and/or NPCs in the non-BI fetch units to prefetch and/or fetch the BI, non-BI, and/or NIs from the disrupted locations; 
 restore values of the BPCs, non-BPCs, and/or NPC stored in the stack to the BPC and/or non-BPC and/or NPC; 
 reset values of the non-BPCs and/or values of NPCs whenever the last NIs of the associated non-BIs are fetched; 
 increase the values of the non-BPCs and/or NPCs whenever a non-BI and/or a NI of the next non-BI are fetched or whenever the first NIs of the associated non-BIs are fetched; 
 repeat resetting and increasing the values of the non-BPCs and/or NPCs until the next non-BIs and/or the last NIs of the non-BIs are fetched; 
 transmit the new NPC values for prefetching BIs to the BI memories and/or caches whenever a single or plurality of branch target addresses is obtained via the BLA branch prediction units in the BLA systems or the interrupt processing units in the backed microprocessors; and 
 transmit the new NPC values for fetching BIs to the BI memories and/or caches whenever a single or plurality of branch target addresses is obtained via the BLA branch prediction units in the BLA systems or the interrupt processing units in the backed microprocessors. 
   
     
     
         16 . The BLA systems of  claim 15 , wherein the single or plurality of BI fetch/decode units is operable to:
 fetch a single or plurality of BIs from the locations received by the BPCs from the BI caches and/or memories via the BI prefetch and fetch systems;   fetch BIs from the BIQs to the BI decode units if the BIQs are used;   store the fetched BIs to a single or plurality of entries of the BIQs by the same BI fetch order if the BIQs are used;   forward the fetched BIs in the BIQs to the BI decode units in the BLA systems if the BIQs are used;   adjust access pointers of the BIQs for writing next fetched BIs to and reading next decoded BIs from the BIQs;   update the next BI addresses to the BPCs in the BI fetch units if the current BIs do not represent any branch instructions fetched;   update the BPCs with a single or plurality of addresses of the BIs at the branch target locations if the current BIs represent the branch instructions fetched;   receive the branch prediction results available a single or plurality of clock cycles ahead from the BLA branch prediction units;   receive a single or plurality of NPC values of BPCs for performing the disrupted operations of the BI fetch and/or decode orders, such as interrupts by the interrupt processing units, branch misprediction corrections by the backend processing engines, and other disrupted operations occurred in microprocessors;   update new NPC values to the BPCs to prefetch and/or fetch the BIs from the disrupted locations;   restore NPC values of the BPC stored in the stack to the BPCs;   forward again the same fetched BIs representing a single or plurality of loops in BIQs to the BI decode units according to the branch prediction results received;   hold the BI fetch operations for fetching any BIs from the BI prefetch/fetch systems whenever forwarding the same fetched BIs representing a single or plurality of loops in BIQs to the BI decode units;   fetch a single or plurality of BIs fetched sequentially or concurrently from the BI memories and caches via the BI prefetch/fetch systems;   store the fetched BIs sequentially or concurrently through a single or plurality of entries of the BIQs;   dispatch the fetched BIs sequentially or concurrently from a single or plurality of entries of the BIQs to the BI decode units;   fetch and dispatch a non-scaled BI representing the non-BI disassembled or a segment of the entire NIs, such as all NIs in a basic block, sequentially;   fetch and dispatch a scaled BI representing a single or plurality of non-BIs disassembled or a single or plurality of sub-segments of the NI segment, such as some NI sub-segments in a basic block, concurrently;   fetch a single non-scaled BI per BI fetch cycle in the BI fetch order to a single entry of BIQ;   fetch a plurality of non-scaled BIs per BI fetch cycle in the BI fetch order to the same plurality of entries of a single BIQ or to the same plurality of single entry BIQs;   fetch a single scaled BI per BI fetch cycle in the BI fetch order to a single entry of BIQ;   fetch a plurality of scaled BIs per BI fetch cycle in the BI fetch order to the same plurality of entries of a single BIQ or to the same plurality of single entry BIQs;   hole a single or plurality of current BI addresses to fetch the BIs from the BI caches and/or memories via the BI prefetch and fetch systems to the BI fetch units in the BLA systems;   update the single or plurality of next BI addresses if the current BIs do not represent any branch instructions fetched;   update the single or plurality of addresses of the BIs at the branch target locations if the current BIs represent the branch instructions fetched;   update values of the single or plurality of current or next BPCs to the stacks in order to resume the disrupted BI operations;   retrieve the NPC values stored in the stacks to the BPCs after the disrupted operations are completed;   receive a single or plurality of fetched BIs from the BI fetch units in the BLA systems;   decode the fetched BIs to provide new non-BPC values for fetching the associated non-BIs to the non-BI fetch units and non-BPCs and/or to provide the NPC values stored in the NPCs in the non-BI fetch units for fetching fixed- and variable-length NIs;   screen any BIs required to be predicted their branch operations and branch target locations;   forward the information for branch prediction to the BLA branch prediction units;   filter BIs representing a single or plurality of loops while forwarding the same BIs representing the same single or plurality of loops to the BAL branch prediction units;   decode the BIs to redirect the associated non-BIs fetched to the non-BIQs in the non-BI fetch units if the fetched non-BIs and/or NIs in the non-BIQs are changed;   transmit the decoded information of the BIs to fetch the associated non-BIs and/or NIs from the non-BI prefetch/fetch systems to the non-BI fetch units or to the non-BIQs in the non-BI fetch units if the non-BIQs are used;   
     
     
         17 . The BLA systems of  claim 14 , wherein the single or plurality of BLA branch prediction units is operable to:
 receive the information for branch prediction from the BI decode units;   access other information for branch prediction from a single or plurality of other useful units found in prior arts including branch predictor and history table;   produce the new NPC values for prefetching and fetching BIs from the BLA systems whenever a single or plurality of branch target addresses is obtained via the BLA branch prediction units in the BLA systems;   transmit the new NPC values for prefetching and fetching BIs to the BI fetch units whenever a single or plurality of branch target addresses is produced; and   update the necessary information for branch prediction to the associated sub-units found in prior arts including branch predictor and history table.   
     
     
         18 . The BLA systems of  claim 14 , wherein the single or plurality of non-BI fetch/decode units is operable to:
 fetch sequentially and/or concurrently the non-BIs and/or NIs addressed by the associated non-BPCs and/or NPCs from the non-BI memories via the levels of non-BI caches;   fetch the non-BIs and/or NIs from the locations addressed by the program counters in the non-BI fetch units whenever the associated non-BPCs and/or NPCs in the non-BI fetch units are updated with new NPC values by decoding the fetched BIs with the BI fetch units;   fetch the non-BIs and/or NIs from the locations received by the NPC values from the branch prediction units whenever a single or plurality of branch target addresses is obtained via the BLA branch prediction units;   fetch the non-BIs and/or NIs from the locations addressed by the interrupt processing units in the backed microprocessors;   fetch the non-BIs and/or NIs from the locations addressed by the backend processing engines in the backed microprocessors for correcting mispredicted branches;   fetch variable-length NIs from the NPC values stored in the NPCs in the non-BI fetch units;   fetch non-BIs and/or NIs from the non-BIQs and/or NIQs to the non-BI decode units if the non-BIQs are used;   store the fetched non-BIs and/or NIs to a single or plurality of entries of the non-BIQs and/or NIQs in the same non-BI and/or NI fetch order if the BIQs are used;   store the fetched NIs to a single or plurality of entries of the NIQs in the same NI fetch order if the BIQs are not used;   forward the fetched non-BIs and/or NIs in the non-BIQs and/or NIQs to the non-BI decode units in the BLA systems if the BIQs are used;   adjust access pointers of the non-BIQs and/or NIQs for writing next fetched non-BIs and/or NIs to and reading next decoded non-BIs and/or NIs from the non-BIQs and/or NIQs;   update the next non-BI and/or NI addresses to the non-BPCs and/or NPCs in the non-BI fetch units if the current non-BIs and/or NIs do not represent any branch instructions fetched;   update the non-BPCs and/or NPCs with a single or plurality of addresses of the non-BIs and/or NIs at the branch target locations if the current non-BIs and/or NIs represent the branch instructions fetched;   receive the branch prediction results available to a single or plurality of clock cycles ahead from the BLA branch prediction units;   receive a single or plurality of NPC values of non-BPCs and/or NPCs for performing the disrupted operations of the non-BI and/or NI fetch and/or decode orders, such as interrupts by the interrupt processing units, branch misprediction corrections by the backend processing engines, and other disrupted operations occurred in microprocessors;   update new NPC values to the non-BPCs and/or NPCs to prefetch and/or fetch the non-BIs and/or NIs from the disrupted locations;   restore NPC values of the non-BPCs and/or NPCs stored in the stack to the non-BPCs and/or NPCs;   forward again the same fetched non-BI and/or NIs representing a single or plurality of loops in the non-BIQs and/or NIQs to the non-BI decode units according to the branch prediction results received;   hold the non-BI and/or NI fetch operations for fetching any non-BIs and/or NIs from the non-BI prefetch/fetch systems whenever forwarding the same fetched non-BIs and/or NIs representing a single or plurality of loops in the non-BIQs and/or NIQs to the non-BI decode units;   fetch a single or plurality of non-BIs and/or NIs fetched sequentially or concurrently from the non-BI memories and caches via the non-BI prefetch/fetch systems;   store the fetched non-BIs and/or NIs sequentially or concurrently through a single or plurality of entries of the non-BIQs and/or NIQs;   dispatch the fetched non-BIs and/or NIs sequentially or concurrently from a single or plurality of entries of the non-BIQs and/or NIQs to the non-BI decode units;   fetch and dispatch a single or plurality of non-scaled non-BIs and/or NIs sequentially;   fetch and dispatch a single or plurality of scaled non-BIs and/or NIs concurrently;   fetch a single non-scaled non-BI per non-BI fetch cycle in the non-BI fetch order to a single entry of non-BIQ;   fetch a plurality of non-scaled non-BIs per non-BI fetch cycle in the non-BI fetch order to the same plurality of entries of a single non-BIQ or to the same plurality of single entry non-BIQs;   fetch a single scaled non-BI per non-BI fetch cycle in the non-BI fetch order to a single entry of non-BIQ for variable-length NIs;   fetch a plurality of scaled non-BIs per non-BI fetch cycle in the non-BI fetch order to the same plurality of entries of a single non-BIQ or to the same plurality of single entry non-BIQs for variable-length NIs;   hole a single or plurality of current non-BI and/or NI addresses to fetch the non-BIs and/or NIs from the non-BI caches and/or memories via the non-BI prefetch and fetch systems to the non-BI fetch units in the BLA systems;   update the single or plurality of next non-BI and/or NI addresses if the current non-BIs and/or NIs do not represent any branch instructions fetched;   update the single or plurality of addresses of the non-BIs and/or NIs at the branch target locations if the current non-BIs and/or NIs represent the branch instructions fetched;   update a single or plurality of current or next non-BPCs' and/or NPCs' values to the stacks in order to resume the disrupted non-BI and/or NI operations;   retrieve the NPC values stored in the stacks to the non-BPCs and/or NPCs after the disrupted operations are completed;   fetch a single or plurality of NIs fetched sequentially or concurrently from the non-BI memories and caches via the non-BI prefetch/fetch systems if any BIs are not fetched;   store the fetched NIs sequentially or concurrently through a single or plurality of entries of the NIQs if any BIs are not fetched;   dispatch the fetched a single or plurality of NIs sequentially or concurrently from a single or plurality of entries of the NIQs to the non-BI decode units if any BIs are not fetched;   fetch and dispatch a single or plurality of NIs sequentially if any BIs are not fetched;   fetch a single non-scaled NI per native fetch cycle in the NI fetch order to a single entry of NIQ for fixed-length NIs;   fetch a plurality of non-scaled NIs per native fetch cycle in the NI fetch order to the same plurality of entries of a single NIQ or to the same plurality of single entry NIQs for fixed-length NIs;   fetch a single scaled NI per native fetch cycle in the NI fetch order to a single entry of NIQ for variable-length NIs;   fetch a plurality of scaled NIs in a plurality of bytes per native fetch cycle in the NI fetch order to the same plurality of entries of a single NIQ or to the same plurality of single entry NIQs for variable-length NIs;   hole a single or plurality of current NI addresses to fetch the NIs from the non-BI caches and/or memories via the non-BI prefetch and fetch systems to the non-BI fetch units in the BLA systems if any BIs are not fetched;   update the single or plurality of next NI addresses if the current NIs do not represent any branch instructions fetched if any BIs are not fetched;   update the single or plurality of addresses of the NIs at the branch target locations if the current NIs represent the branch instructions fetched if any BIs are not fetched;   update a single or plurality of current or next NPCs' values to the stacks in order to resume the disrupted NI operations if any BIs are not fetched;   retrieve the NPC values stored in the stacks to the NPCs after the disrupted operations are completed if any BIs are not fetched;   receive a single or plurality of fetched non-BIs and/or NIs from the non-BI fetch units in the BLA systems;   decode the fetched non-BIs and/or native conditional branch instructions to provide new values of the non-BPCs and/or NPCs for fetching the non-BIs and/or fixed- and variable-length NIs to the non-BI fetch units;   screen any non-BIs and/or NIs required to be predicted their branch operations and branch target locations if any BIs are not fetched;   forward the information for branch prediction to the non-BIs and/or native branch prediction units if any BIs are not fetched;   filter non-BIs and/or NIs representing a single or plurality of loops while forwarding the same non-BIs and/or NIs representing the same single or plurality of loops to the non-BI and/or native branch prediction units if any BIs are not fetched; and   transmit the decoded information of the non-BIs and/or NIs to fetch the associated non-BIs and/or NIs from the non-BI prefetch/fetch systems to the non-BI fetch units if any BIs are not fetched or to the non-BIQs in the non-BI fetch units if the non-BIQs are used and any BIs are not fetched.