US2016277027A1PendingUtilityA1

Dynamic impedance control for input/output buffers

Assignee: CONVERSANT INTELLECTUAL PROPERTY MAN INCPriority: Jun 8, 2007Filed: Mar 24, 2016Published: Sep 22, 2016
Est. expiryJun 8, 2027(~0.9 yrs left)· nominal 20-yr term from priority
Inventors:Bruce Millar
H03K 19/0005G11C 11/4093H03H 17/0045G11C 29/028H04L 25/028H03H 7/38G11C 7/1084G11C 7/1057G11C 7/1051G11C 7/1078G11C 2207/2254H04L 25/0278G11C 7/02G11C 5/063
53
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

A system and method of performing off chip drive (OCD) and on-die termination (ODT) are provided. A common pull-up network composed of transistors and a common pull-down network composed of transistors are employed to implement both of these functions. In drive mode, the pull-up network is configured to produce a calibrated drive impedance when an “on” output is to be generated, and the pull-up network is configured to produce a calibrated drive impedance when an “off” output is to be generated. In termination mode, the pull-up network and the pull-down network are configured to produce a calibrated pull-up resistance and pull-down resistance respectively such that together, they form a split termination.

Claims

exact text as granted — not AI-modified
1 . A system comprising:
 a circuit comprising:
 a first plurality of transistors connected in parallel between a first power supply and a data output terminal; 
 a first plurality of OCD configuration bits; 
 a first plurality of ODT configuration bits; and 
 logic for driving the gate of each of the first plurality of transistors based on the OCD and ODT configuration bits,
 the logic being configurable in an OCD mode to drive a gate of each of the first plurality of transistors based on a state of a respective one of the first plurality of OCD configuration bits to generate a first OCD impedance; 
 the logic being configurable in an ODT mode to drive a gate of each of the first plurality of transistors based on a state of a respective one of the first plurality of ODT configuration bits to generate a first ODT impedance; 
 
 wherein the first plurality of transistors dynamically switches between the first OCD impedance and the first ODT impedance based on an enable signal. 
   
     
     
         2 . The system of  claim 1 , wherein the circuit further comprises a resistor connected between the first plurality of transistors and the data output terminal. 
     
     
         3 . The system of  claim 2 , wherein the resistor is a diffusion resistor.

Join the waitlist — get patent alerts

Track US2016277027A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.