Method of forming an on-pitch self-aligned hard mask for contact to a tunnel junction using ion beam etching

Abstract

A method of forming a memory device that in one embodiment may include forming a magnetic tunnel junction on a first electrode using an electrically conductive mask and subtractive etch method. Following formation of the magnetic tunnel junction, at least one dielectric layer is deposited to encapsulate the magnetic tunnel junction. Ion beam etching/Ion beam milling may then remove the portion of the at least one dielectric layer that is present on the electrically conductive mask, wherein a remaining portion of the at least one dielectric layer is present over the first electrode. A second electrode may then be formed in contact with the electrically conductive mask.

What is claimed is: 
     
         1 . A memory device comprising:
 a first electrode present on a substrate;   a magnetic tunnel junction present on the first electrode;   an electrically conductive mask present on an upper surface of the magnetic tunnel junction;   at least one dielectric layer present on exposed portions of the substrate and the first electrode that are present adjacent to the magnetic tunnel junction, a sidewall of the magnetic tunnel junction, and at least a portion of a sidewall of the electrically conductive mask, wherein a dimension extending from an upper surface of the magnetic tunnel junction to the first electrode is greater than a height of the at least one dielectric layer that is present on said portion of the sidewall of the electrically conductive mask; and   a second electrode is present on the electrically conductive mask.   
     
     
         2 . The memory device of  claim 1 , wherein the magnetic tunnel junction comprises a first ferromagnetic plate that is present on the first electrode, a dielectric layer that is present on the first ferromagnetic plate, and a second ferromagnetic plate that is present on the dielectric layer. 
     
     
         3 . The memory device of  claim 2 , wherein the first ferromagnetic plate comprises a composition selected from the group consisting of nickel iron (NiFe), cobalt iron (CoFe), iridium-manganese (IrMn), platinum manganese (PtMn), ruthenium (Ru), cobalt iron boron (CoFeB),chromium molybdenum (CrMo), tantalum (Ta), tantalum nitride (TaN), and combinations thereof. 
     
     
         4 . The memory device of  claim 2 , wherein the dielectric layer is selected from the group consisting of aluminum oxide (Al 2 O 3 ), magnesium oxide (MgO), boron nitride (BN), silicon oxide (SiO 2 ) and combinations thereof. 
     
     
         5 . The memory device of  claim 2 , wherein the second ferromagnetic plate comprises a composition selected from the group consisting of nickel iron (NiFe), cobalt iron (CoFe), iridium-manganese (IrMn), platinum manganese (PtMn), ruthenium (Ru), cobalt iron boron (CoFeB),chromium molybdenum (CrMo), tantalum (Ta), tantalum nitride (TaN), and combinations thereof. 
     
     
         6 . The memory device of  claim 2 , wherein the electrically conductive mask has a composition that is selected from the group consisting of copper (Cu), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), aluminum (Al), tungsten (W) and combinations thereof. 
     
     
         7 . The memory device of  claim 2 , wherein the difference in height between the upper surface of the at least one dielectric layer and an upper surface of the electrically conductive mask ranges from 1 nm to 50 nm. 
     
     
         8 . The memory device of  claim 2 , wherein the memory device is a spin torque transfer random access memory (STTRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), phase change random access memory (PCRAM), carbon nanotube random access memory (NRAM), resistive random access memory (RRAM), copper bridge random access memory (CBRAM), polymer RAM, or a combinations thereof. 
     
     
         9 . A memory device comprising:
 a first electrode present on a substrate;   a magnetic tunnel junction comprising a first ferromagnetic plate that is present on the first electrode, a dielectric layer that is present on the first ferromagnetic plate, and a second ferromagnetic plate that is present on the dielectric layer;   an electrically conductive mask present on an upper surface of the magnetic tunnel junction;   at least one dielectric layer present on exposed portions of the substrate and the first electrode that are present adjacent to the magnetic tunnel junction, a sidewall of the magnetic tunnel junction, and at least a portion of a sidewall of the electrically conductive mask, wherein a dimension extending from an upper surface of the magnetic tunnel junction to the first electrode is greater than a height of the at least one dielectric layer that is present on said portion of the sidewall of the electrically conductive mask; and   a second electrode is present on the electrically conductive mask.   
     
     
         10 . The memory device of  claim 9 , wherein the first ferromagnetic plate comprises a composition selected from the group consisting of nickel iron (NiFe), cobalt iron (CoFe), iridium-manganese (IrMn), platinum manganese (PtMn), ruthenium (Ru), cobalt iron boron (CoFeB),chromium molybdenum (CrMo), tantalum (Ta), tantalum nitride (TaN), and combinations thereof. 
     
     
         11 . The memory device of  claim 10 , wherein the dielectric layer is selected from the group consisting of aluminum oxide (Al 2 O 3 ), magnesium oxide (MgO), boron nitride (BN), silicon oxide (SiO 2 ) and combinations thereof. 
     
     
         12 . The memory device of  claim 10 , wherein the second ferromagnetic plate comprises a composition selected from the group consisting of nickel iron (NiFe), cobalt iron (CoFe), iridium-manganese (IrMn), platinum manganese (PtMn), ruthenium (Ru), cobalt iron boron (CoFeB),chromium molybdenum (CrMo), tantalum (Ta), tantalum nitride (TaN), and combinations thereof. 
     
     
         13 . The memory device of  claim 10 , wherein the electrically conductive mask has a composition that is selected from the group consisting of copper (Cu), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), aluminum (Al), tungsten (W) and combinations thereof. 
     
     
         14 . The memory device of  claim 10 , wherein the difference in height between the upper surface of the at least one dielectric layer and an upper surface of the electrically conductive mask ranges from 1 nm to 50 nm. 
     
     
         15 . The memory device of  claim 10 , wherein the memory device is a spin torque transfer random access memory (STTRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), phase change random access memory (PCRAM), carbon nanotube random access memory (NRAM), resistive random access memory (RRAM), copper bridge random access memory (CBRAM), polymer RAM, or a combinations thereof. 
     
     
         16 . A memory device comprising:
 a first electrode present on a substrate;   a magnetic tunnel junction present on the first electrode;   an electrically conductive mask present on an upper surface of the magnetic tunnel junction;   at least one dielectric layer present on exposed portions of the substrate and the first electrode that are present adjacent to the magnetic tunnel junction, a sidewall of the magnetic tunnel junction, and at least a portion of a sidewall of the electrically conductive mask, wherein a dimension extending from an upper surface of the magnetic tunnel junction to the first electrode is greater than a height of the at least one dielectric layer that is present on said portion of the sidewall of the electrically conductive mask, wherein the difference in height between the upper surface of the at least one dielectric layer and an upper surface of the electrically conductive mask ranges from 10 nm to 50 nm; and   a second electrode is present on the electrically conductive mask.   
     
     
         17 . The memory device of  claim 16 , wherein the magnetic tunnel junction comprises a first ferromagnetic plate that is present on the first electrode, a dielectric layer that is present on the first ferromagnetic plate, and a second ferromagnetic plate that is present on the dielectric layer. 
     
     
         18 . The memory device of  claim 17 , wherein the first ferromagnetic plate comprises a composition selected from the group consisting of nickel iron (NiFe), cobalt iron (CoFe), iridium-manganese (IrMn), platinum manganese (PtMn), ruthenium (Ru), cobalt iron boron (CoFeB),chromium molybdenum (CrMo), tantalum (Ta), tantalum nitride (TaN), and combinations thereof. 
     
     
         19 . The memory device of  claim 17 , wherein the dielectric layer is selected from the group consisting of aluminum oxide (Al 2 O 3 ), magnesium oxide (MgO), boron nitride (BN), silicon oxide (SiO 2 ) and combinations thereof. 
     
     
         20 . The memory device of  claim 17 , wherein the second ferromagnetic plate comprises a composition selected from the group consisting of nickel iron (NiFe), cobalt iron (CoFe), iridium-manganese (IrMn), platinum manganese (PtMn), ruthenium (Ru), cobalt iron boron (CoFeB),chromium molybdenum (CrMo), tantalum (Ta), tantalum nitride (TaN), and combinations thereof.