Output capacitance reduction in power transistors

Abstract

Technologies are described for reduction of an output capacitance of a transistor. In some examples, spacing of source-to-drain metallization may be increased and a sealed air-gap may be employed in an elongated trench in the drain region to reduce a dielectric constant of a portion of the body region and thereby the output capacitance of the transistor. In other examples, a planar area component of a body-drain junction may be reduced by forming a spherical cavity at a bottom portion of the body-drain junction and sealing the cavity with a low dielectric constant material. In further examples, a sealed cavity may be formed in an epitaxial region below the body region through formation and removal of selective buried oxide islands. In yet other examples, the output capacitance may be reduced through removal of areas in the drain region of the transistor that do not contribute to the current flow.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a substrate;   an epitaxial layer in contact with a surface of the substrate;   a nitride layer in contact with a surface of the epitaxial layer;   a body region within a top portion of the epitaxial layer;   a source region within the top portion of the epitaxial layer, the source region electrically coupled to the body region; and   a drain region within the epitaxial layer, wherein the epitaxial layer includes a cavity region below the nitride layer between the drain region and the body region such that a planar drift distance between the drain region and the source region is increased by two or more dimensions of the cavity region.   
     
     
         2 . The semiconductor device of  claim 1 , further comprising:
 an oxide layer in contact with the nitride layer;   a dielectric layer in contact with the oxide layer,   one or more interlayer dielectric layers in contact with the dielectric layer; and   a contact layer, wherein a first portion of the contact layer is in contact with the source region such that a distance between the drain region and the first portion of the contact layer is increased by a vertical dimension of the cavity region.   
     
     
         3 . The semiconductor device of  claim 2 , further comprising:
 another drain region within the epitaxial layer, and   another cavity region below the nitride layer, wherein the body region is centrally located within the top portion of the epitaxial layer between the drain region and the another drain region.   
     
     
         4 . The semiconductor device of  claim 3 , wherein the contact layer further includes a second portion in contact with the drain region and a third portion in contact with the another drain region, the first, second, and third portions separated by passivation layers. 
     
     
         5 . The semiconductor device of  claim 1 , wherein at least one of:
 a width of the cavity region is in a range from about 3 micrometers to about 20 micrometers; and   a height of the cavity region is in a range from about 0.5 micrometers to about 5 micrometers.   
     
     
         6 . The semiconductor device of  claim 1 , wherein the cavity region has a substantially trapezoidal shape. 
     
     
         7 . The semiconductor device of  claim 1 , wherein the semiconductor device comprises one of a lateral transistor, a lateral power transistor, a lateral radio frequency (RF) power transistor, or a lateral double-diffused metal oxide semiconductor (LDMOS). 
     
     
         8 . The semiconductor device of  claim 1 , further comprising:
 a conductive shield layer that substantially covers a top surface of the epitaxial layer and the cavity region;   an oxide layer in contact with the conductive shield layer; and   a dielectric layer in contact with the oxide layer.   
     
     
         9 . The semiconductor device of  claim 1 , wherein a diameter of the cavity region is in a range from about 1 micrometer to about 5 micrometers. 
     
     
         10 . A semiconductor device, comprising:
 a substrate;   an epitaxial layer in contact with a top surface of the substrate;   a drain layer in the substrate;   a body region within a top portion of the epitaxial layer;   a source region within a top portion of the body region;   a vertical gate structure substantially along at least one outer edge of the body region; and   a substantially spherical cavity region within the epitaxial layer and a bottom portion of the body region, wherein the cavity region is configured to lower a contribution of the body region to an output capacitance of the semiconductor device with a reduced effect on a current flow through the body region.   
     
     
         11 . The semiconductor device of  claim 10 , further comprising:
 two trenches on opposite sides of the body region in the top portion of the epitaxial layer, the trenches filled with a dielectric material;   a conductive shield layer that substantially covers the top surface of the epitaxial layer and at least one of the trenches;   an oxide layer in contact with the shield layer;   a dielectric layer in contact with the oxide layer;   one or more interlayer dielectric layers in contact with the dielectric layer; and   a contact layer, wherein a first portion of the contact layer is in contact with the gate structure and a second portion of the contact layer is in contact with the source region and the shield layer.   
     
     
         12 . The semiconductor device of  claim 10 , wherein the cavity region is sealed with a dielectric material at a top portion. 
     
     
         13 . The semiconductor device of  claim 10 , wherein a diameter of the cavity region is in a range from about 1 micrometer to about 5 micrometers. 
     
     
         14 . The semiconductor device of  claim 10 , wherein the semiconductor device is one of: a vertical transistor, a lateral transistor, a vertical gate shielded power transistor, or a lateral gate shielded power transistor. 
     
     
         15 . A semiconductor device, comprising:
 a substrate;   an epitaxial layer in contact with a top surface of the substrate;   a drain layer in the substrate;   a body region within a top portion of the epitaxial layer;   a source region within a top portion of the body region;   a vertical gate structure substantially along at least one outer edge of the body region; and   a substantially T-shaped cavity region within the epitaxial layer and a bottom portion of the body region, wherein the cavity region is configured to lower a contribution of the body region to an output capacitance of the semiconductor device with a reduced effect on a current flow through the body region.   
     
     
         16 . The semiconductor device of  claim 15 , further comprising:
 two trenches on opposite sides of the body region in the top portion of the epitaxial layer, the trenches filled with a dielectric material;   a conductive shield layer that substantially covers a top surface of the epitaxial layer and at least one of the trenches;   an oxide layer in contact with the shield layer;   a dielectric layer in contact with the oxide layer;   one or more interlayer dielectric layers in contact with the dielectric layer; and   a contact layer, wherein a first portion of the contact layer is in contact with the gate structure and a second portion of the contact layer is in contact with the source region and the shield layer.   
     
     
         17 . The semiconductor device of  claim 15 , wherein a width of a top portion of the cavity region is substantially equal to a width of the body region. 
     
     
         18 . The semiconductor device of  claim 15 , wherein one or more of:
 a width of a top portion of the cavity region below the body region is in a range from about 1 micrometers to about 10 micrometers; and   a length of a top portion of the cavity region is in a range from about 1 micrometers to about 200 micrometers.