Semiconductor device and manufacturing process thereof

Abstract

A semiconductor device is provided which includes a dielectric layer over a gate structure of the semiconductor device. The semiconductor device also includes a conductive interconnect configured to couple the gate structure with an I/O region over the conductive interconnect. The semiconductor also includes a metal silicide layer disposed between the conductive interconnect and the dielectric layer where the metal silicide is a silicide form of a metal different from the conductive interconnect.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a dielectric layer over a gate structure of the semiconductor device;   a conductive interconnect configured to couple the gate structure with an I/O region over the conductive interconnect; and   a metal silicide layer disposed above the conductive interconnect and the dielectric layer, the metal silicide being a silicide form of a first metal different from the conductive interconnect, and the metal silicide layer comprising a sidewall substantially coplanar with a side wall of the conductive interconnect.   
     
     
         2 . The semiconductor device according to  claim 1  further comprising a conductive layer disposed between the conductive interconnect and the metal silicide layer, wherein the conductive layer is the first metal. 
     
     
         3 . The semiconductor device according to  claim 2  further comprising a silicon layer inside the dielectric layer, wherein the silicon layer is between the metal silicide layer and the dielectric layer. 
     
     
         4 . The semiconductor device according to  claim 3 , wherein the silicon layer is further disposed on a periphery of the metal silicide layer. 
     
     
         5 . The semiconductor device according to  claim 1 , wherein the coefficient of linear thermal expansion (CTE-l) of the conductive interconnect is larger than the CTE of the metal silicide layer, and the CTE-l of the metal silicide layer is larger than the CTE-l of the dielectric layer. 
     
     
         6 . The semiconductor device according to  claim 2 , wherein the conductive layer includes one of cobalt, nickel, tungsten, molybdenum, titanium, platinum and tantalum. 
     
     
         7 . The semiconductor device according to  claim 1 , wherein the conductive interconnect includes copper. 
     
     
         8 . The semiconductor device according to  claim 1 , wherein a ratio of thickness between the dielectric layer and the metal silicide layer is between 1 and 200. 
     
     
         9 . A semiconductor device, comprising:
 a first dielectric layer;   a conductive interconnect disposed within the first dielectric layer;   a metal silicide layer disposed over the conductive interconnect;   a silicon layer disposed on a periphery of the metal silicide layer; and   a second dielectric layer disposed over the metal silicide layer and the silicon layer, the second dielectric layer covering a top surface of the metal silicide layer.   
     
     
         10 . The semiconductor device according to  claim 9 , wherein the silicon layer is disposed between the metal silicide layer and the second dielectric layer. 
     
     
         11 . The semiconductor device according to  claim 9 , wherein the coefficient of linear thermal expansion (CTE-l) of the conductive interconnect is larger than CTE-l of the metal silicide layer, and the CTE-l of the metal silicide layer is larger than the CTE-l of the first and the second dielectric layers. 
     
     
         12 . The semiconductor device according to  claim 9 , wherein the conductive interconnect includes a first metal, and the metal silicide layer is a silicide form of a second metal different from the first metal. 
     
     
         13 . The semiconductor device according to  claim 12 , wherein the second metal includes one of cobalt, nickel, tungsten, molybdenum, titanium, platinum and tantalum. 
     
     
         14 . The semiconductor device according to  claim 12  further comprising a conductive layer including the second metal, disposed between the conductive interconnect and the metal silicide layer. 
     
     
         15 . (canceled) 
     
     
         16 . (canceled) 
     
     
         17 . (canceled) 
     
     
         18 . (canceled) 
     
     
         19 . (canceled) 
     
     
         20 . (canceled) 
     
     
         21 . A semiconductor device, comprising:
 a dielectric layer over a gate structure of the semiconductor device;   a conductive interconnect disposed within the dielectric layer;   a metal silicide layer disposed over the conductive interconnect; and   a silicon layer disposed on a periphery of the metal silicide layer and covering the dielectric layer.   
     
     
         22 . The semiconductor device according to  claim 21 , wherein the coefficient of linear thermal expansion (CTE-l) of the conductive interconnect is larger than the CTE-l of the metal silicide layer, and the CTE-l of the metal silicide layer is larger than the CTE-l of the dielectric layer. 
     
     
         23 . The semiconductor device according to  claim 21 , wherein the metal silicide layer is a silicide form of a metal selected from one of cobalt, nickel, tungsten, molybdenum, titanium, platinum and tantalum. 
     
     
         24 . The semiconductor device according to  claim 21 , wherein the conductive interconnect includes copper. 
     
     
         25 . The semiconductor device according to  claim 21 , wherein a ratio of thickness between the dielectric layer and the metal silicide layer is between 1 and 200. 
     
     
         26 . The semiconductor device according to  claim 21 , wherein the conductive interconnect includes a first metal, and the metal silicide layer is a silicide form of a second metal different from the first metal.