Computing architecture with peripherals

Abstract

A shared memory computing device optimised for worst case execution time analysis that has at least one interconnect master, N cache modules and N processor cores. Each cache module has a finite state machine that employs an update-type cache coherency policy. Each processor core is assigned a different one of the N fully associative cache modules as its private cache. Furthermore, the execution time of memory transfer requests issued by each of the N processor cores is not modified by: (a) the unrelated memory transfer requests issued by any of the other N processor cores; or (b) the unrelated memory transfer requests issued by at least one other interconnect master.

1 . A shared memory computing device comprising:
 a first clock;   at least M interconnect masters, where the value of M is 4;   at least 1 interconnect target;   a first timeslot based interconnect for transporting memory transfer requests and their corresponding responses, comprising:
 an input clock port that is connected to the first clock; 
 a unidirectional timeslot based interconnect to transport memory transfer requests with T timeslots, where the value of T is at least 4; 
 a unidirectional timeslot based interconnect to transport memory transfer responses with R timeslots, in which:
 for each of the R timeslots that timeslot:
 corresponds to one memory transfer request timeslot; and 
 starts at least L clock cycles after the start time of that 
 corresponding memory request timeslot, where the value of L is at least 3 and less than the value of T; 
 
 
   in which:
 at least one interconnect target is connected to the first timeslot based interconnect; and 
 for each interconnect master I of the M interconnect masters:
 each interconnect master I is connected to the first timeslot based interconnect; and 
 each of the T timeslots is mappable to a different one of the M interconnect masters. 
 
   
     
     
         2 . A shared memory computing device as claimed in  claim 1 , in which the value of R equals the value of T, and each of the T memory transfer request timeslots on the first timeslot based interconnect has a corresponding memory transfer response timeslot of the same length on that interconnect. 
     
     
         3 . A shared memory computing device as claimed in  claim 1  or  claim 2 , in which there are at least 2 interconnect targets and the first timeslot based interconnect further comprises a means to enforce an access control policy between interconnect masters and interconnect targets. 
     
     
         4 . A shared memory computing device as claimed in  claim 3 , in which the means to enforce an access control policy is adapted to ensure that no more than one interconnect master can issue memory transfer requests to any given interconnect target. 
     
     
         5 . A shared memory computing device as claimed in any one of  claims 1  to  4 , further comprising:
 an on-chip random access memory store, comprising:
 an input clock port that is connected to the first clock; and 
 at least one interconnect target port which is connected to the first timeslot based interconnect, and in which:
 each memory transfer request takes at most K clock cycles to complete under fault-free operation, where the value of K is less than or equal to the value of L; and 
 that target port can sustain a throughput of 1 memory transfer request per clock cycle. 
 
 
 
     
     
         6 . A shared memory computing device as claimed in any one of the  claims 1  to  3  in which one of the M interconnect masters is an interconnect protocol transcoding bridge in which the protocol to transcode is a bus protocol. 
     
     
         7 . A process emulating a shared memory computing device as claimed in any one of  claims 1  to  6 . 
     
     
         8 . A process adapted to control a shared memory computing device as claimed in any one of  claims 1  to  6 . 
     
     
         9 . A signal carrying a representation in a hardware description language of a shared memory computing device as claimed in any one of  claims 1  to  6 . 
     
     
         10 . A machine readable substrate carrying a representation in a hardware description language of a shared memory computing device as claimed in any one of  claims 1  to  6 . 
     
     
         11 . A shared memory computing device optimised for upper-bound worst case execution time analysis comprising:
 an on-chip random access memory store comprising at least two interconnect target ports, in which:
 the first target port:
 has a data path of D-bits in width, the value of D being larger than or equal to 2; 
 is adapted to sustain a throughput of one D-bit wide memory transfer request per clock cycle; and 
 is adapted to sustain a throughput of one D-bit wide memory transfer response per clock cycle; and 
 
 the second target port:
 has a data path of E-bits in width, the value of E being larger than or equal to 1; 
 is adapted to sustain a throughput of one E-bit wide memory transfer request per clock cycle; and 
 is adapted to sustain a throughput of one E-bit wide memory transfer response per clock cycle; 
 
   a first on-chip shared memory interconnect which:
 has a data path of D-bits in width; 
 is exclusively connected to the first port of the at least two interconnect target ports of the on-chip random access memory; 
 is adapted to sustain a throughput of one D-bit wide memory transfer request per clock cycle to the on-chip random access memory; 
 is adapted to sustain a throughput of one D-bit wide memory transfer response per clock cycle; and 
 has at least two cache modules connected to it, each cache module comprising:
 a master port with a D-bit wide data path which is connected to this interconnect; and 
 a target port; 
 
   and a second on-chip shared memory interconnect which:
 has a data path of E-bits in width; 
 is exclusively connected to the second port of the at least two interconnect target ports of the on-chip random access memory; 
 is adapted to sustain a peak throughput of one E-bit wide memory transfer request per clock cycle to the on-chip random access memory; and 
 is adapted to sustain a peak throughput of one E-bit wide memory transfer response per clock cycle; and 
 has at least two interconnect masters connected to it. 
   
     
     
         12 . A shared memory computing device as claimed in  claim 1 , in which at least 2 of the at least 2 cache modules which are connected to the first on-chip shared memory interconnect maintain cache-coherency with each other with zero timing interference to unrelated memory transfer requests received on the target port of those at least 2 cache modules. 
     
     
         13 . A shared memory computing device as claimed in  claim 11  or  claim 12 , in which at least 2 of the at least 2 cache modules which are connected to the first on-chip shared memory interconnect operate in a cache-coherency group that maintains cache-coherency between each other and also maintains cache coherency against the write memory transfer requests issued to at least one of the other ports of the on-chip random access memory. 
     
     
         14 . A shared memory computing device as claimed in any one of  claims 11  to  13 , in which at least 2 of the at least 2 cache modules which are connected to the first on-chip shared memory interconnect operate in a cache-coherency group that maintains cache-coherency between each other are update type of caches that snarf each others write requests. 
     
     
         15 . A shared memory computing device as claimed in any one of  claims 11  to  14 , in which:
 both the first and second on-chip shared memory interconnects employ timeslot based arbitration schemes; and 
 at least two timeslots of the first on-chip shared memory interconnect each have a timeslot length of one clock cycle in length. 
 
     
     
         16 . A shared memory computing device as claimed in any one of  claims 11  to  15 , further comprising:
 at least one processor core; 
 a first peripheral, comprising:
 a first interconnect target port which is connected to the first on-chip shared memory interconnect; and 
 a first interconnect master port which is connected to the second on-chip shared memory interconnect; 
 
 in which:
 at least one of the at least one processor cores can issue a memory transfer request over the first on-chip shared memory interconnect to the first peripheral; 
 the first peripheral can store data in the on-chip random access memory; and 
 the at least one of the at least one processor cores can read that data. 
 
 
     
     
         17 . A shared memory computing device as claimed in any one of  claims 11  to  16 , further comprising:
 at least one processor core; 
 a first peripheral interconnect for transporting memory transfer requests and their corresponding responses; 
 a first peripheral, comprising:
 a first interconnect target port which is connected to the first peripheral interconnect; and 
 a first interconnect master port which is connected to one of the at least two on-chip shared memory interconnects; 
 
 in which:
 at least one of the at least one processor cores can issue a memory transfer request over the first peripheral interconnect to the first peripheral; 
 the first peripheral can store data in the on-chip random access memory; and 
 the at least one of the at least one processor cores can read that data. 
 
 
     
     
         18 . A shared memory computing device as claimed in  17 , further comprising at least one interconnect for transporting cache coherency traffic, in which at least 2 of the at least 2 cache modules that maintain cache coherency are connected to the same interconnect of the at least one interconnect for transporting cache coherency traffic. 
     
     
         19 . A shared memory computing device as claimed in any one of the  claims 11  to  18  in which one of the interconnect masters attached to one of the two on-chip shared memory interconnects is an interconnect protocol transcoding bridge. 
     
     
         20 . A process emulating a shared memory computing device as claimed in any one of  claims 11  to  19 . 
     
     
         21 . A process adapted to control a shared memory computing device as claimed in any one of  claims 11  to  19 . 
     
     
         22 . A signal carrying a representation in a hardware description language of a shared memory computing device as claimed in any one of  claims 11  to  19 . 
     
     
         23 . A machine readable substrate carrying a representation in a hardware description language of a shared memory computing device as claimed in any one of  claims 11  to  19 . 
     
     
         24 . A shared memory computing device comprising:
 a first system interconnect;   an on-chip random access memory store comprising at least one interconnect target port,   in which the first interconnect target port is connected to the first system interconnect;   at least one sub-computing device, each sub-computing device comprising:
 a first local interconnect; 
 a first interconnect master connected to a local interconnect of the sub-computing device; 
 an interconnect bridge comprising two ports, in which:
 the first port is connected to the first system interconnect; and 
 the second port is connected to a local interconnect of the sub-computing device; and 
 
 in which the first interconnect master is adapted to issue memory transfer requests to the on-chip random access memory store; and 
   a first peripheral, comprising:
 a first interconnect target port which is connected to the first local interconnect of the first of the at least one sub-computing devices; 
 a first interconnect master port which is adapted to issue memory transfer requests to the on-chip random access memory store; 
   in which:
 the first interconnect master of the first of the at least one sub-computing devices is adapted to issue memory transfer requests to the first peripheral. 
   
     
     
         25 . A shared memory computing device as claimed in  claim 24 , in which there are at least two sub-computing devices and the first peripheral further comprises:
 a second interconnect target port which is connected to the first local interconnect of a second of the at least one sub-computing devices; and   the first interconnect master of the second of the at least two sub-computing devices is adapted to issue memory transfer requests to the first peripheral.   
     
     
         26 . A shared memory computing device as claimed in  claim 24  or  claim 25 , in which there are at least two sub-computing devices and further comprising:
 a second peripheral, comprising a first interconnect target port which is connected to the first system interconnect; 
 in which the first interconnect master of at least two of the at least two sub-computing devices is adapted to issue memory transfer requests to the second peripheral. 
 
     
     
         27 . A shared memory computing device as claimed in  claim 26  in which the second peripheral further comprises a first interconnect master which is adapted to issue memory transfer requests to the on-chip random access memory. 
     
     
         28 . A shared memory computing device as claimed in any one of  claims 24  to  27 , further comprising a second system interconnect in which:
 the on-chip random access memory store has at least two interconnect target ports; 
 the second interconnect target port of the random access memory store is connected to the second system interconnect; and 
 the first interconnect master port of the first peripheral is connected to the second system interconnect. 
 
     
     
         29 . A shared memory computing device as claimed in  claim 28  in which the first interconnect master port of the second peripheral is connected to the second system interconnect. 
     
     
         30 . A shared memory computing device as claimed in any one of  claims 24  to  29  in which the first system interconnect is a timeslot based interconnect. 
     
     
         31 . A process emulating a shared memory computing device as claimed in any one of  claims 24  to  30 . 
     
     
         32 . A process adapted to control a shared memory computing device as claimed in any one of  claims 24  to  30 . 
     
     
         33 . A signal carrying a representation in a hardware description language of a shared memory computing device as claimed in any one of  claims 24  to  30 . 
     
     
         34 . A machine readable substrate carrying a representation in a hardware description language of a shared memory computing device as claimed in any one of  claims 24  to  30 . 
     
     
         35 . A shared memory computing device comprising:
 M interconnect-masters, where the value of M is at least 2, each interconnect-master comprising:
 an egress port; and 
 an ingress port; and 
   a first timeslot based interconnect for transporting memory transfer requests and their corresponding responses, comprising:
 an arbiter and decoder module; 
 a M-to-1 multiplexer, comprising:
 a select port; 
 M data input ports; and 
 1 data output port; 
 
 and a 1-to-M demultiplexer, comprising:
 a select port; 
 1 data input port; and 
 M data output ports; 
 
   
       in which:
 for each interconnect master I:
 the egress port of interconnect master I is connected to the data input port I of the M-to-1 multiplexer; and 
 the ingress port of interconnect master I is connected to the data output port I of the 1-to-M demultiplexer; 
 
 the arbiter and decoder module of the interconnect controls the value supplied to the select port of the M-to-1 multiplexer; and 
 the value supplied to the select port of the 1-to-M demultiplexer is the value supplied to the select port of the M-to-1 multiplexer delayed by L clock cycles, where the value of L is larger or equal to 3. 
 
     
     
         36 . A shared memory computing device as claimed in  claim 35  in which each timeslot of the first timeslot based interconnect has a variable duration of length that is upper-bound for that timeslot. 
     
     
         37 . A shared memory computing device as claimed in  claim 36  in which the duration of least one timeslot of the first timeslot based interconnect is 1 clock cycle in length. 
     
     
         38 . A shared memory computing device as claimed in any one of  claims 35  to  37 , further comprising:
 S interconnect-targets, where the value of S is at least 2, each interconnect-target comprising:
 an egress port; and 
 an ingress port; 
 
 
       in which the first timeslot based interconnect for transporting memory transfer requests and their corresponding responses further comprises:
 a 1-to-S demultiplexer, comprising:
 a select port; 
 1 data input port; and 
 S data output ports; and 
 
 a S-to-1 multiplexer, comprising:
 a select port; 
 S data input ports; and 
 1 data output port; 
 
 
       in which:
 the data input port of the 1-to-S demultiplexer receives as input the output of the M-to-1 multiplexer, 
 the data input port of the 1-to-M demultiplexer receives as input the output of the S-to-1 multiplexer; 
 for each interconnect target J:
 the ingress port of interconnect target J is connected to the data output port I of the 1-to-S demultiplexer, and 
 the egress port of interconnect target J is connected to the data input port S of the S-to-1 multiplexer; and 
 
 the arbiter and decoder module of the interconnect controls the value supplied to the select port of the 1-to-S demultiplexer; and 
 the value supplied to the select port of the S-to-1 multiplexer is the value supplied to the select port of the 1-to-S demultiplexer delayed by L clock cycles. 
 
     
     
         39 . A shared memory computing device as claimed in any one of  claims 35  to  38 , in which the first timeslot based interconnect further comprises a means to enforce an access control policy between interconnect masters and interconnect targets. 
     
     
         40 . A shared memory computing device as claimed in  claim 39 , in which the means to enforce an access control policy is adapted to ensure that no more than one interconnect master can issue memory transfer requests to any given interconnect target. 
     
     
         41 . A shared memory computing device as claimed in any one of  claims 35  to  40  in which the interconnect master is an interconnect protocol transcoding bridge; 
     
     
         42 . A shared memory computing device as claimed in any one of  claims 35  to  41 , in which:
 the arbiter and decoder module of the first timeslot based interconnect is adapted to:
 grant a first timeslot to one of the M interconnect masters; 
 not grant the next timeslot to that interconnect master; and 
 grant one of the later timeslots to the that interconnect master; 
 
 the first interconnect master is adapted to:
 issue a memory transfer request to a first interconnect target during the first timeslot; and 
 
 the first interconnect target is adapted to:
 transmit at least part of its response to the first interconnect master during the later timeslot granted to the first interconnect master. 
 
 
     
     
         43 . A shared memory computing device as claimed in any one of  claims 35  to  42 , in which the arbiter and decoder module of the first timeslot based interconnect employs at least one scheduling scheme selected from the group comprising:
 a least recently granted interconnect master scheme; 
 a least recently granted interconnect master scheme with rate throttling on at least one interconnect master; 
 a static timeslot scheme; 
 a dynamic timeslot scheme; and 
 a time triggered protocol scheme. 
 
     
     
         44 . A shared memory computing device as claimed in any one of  claims 35  to  43 , further comprising:
 an on-chip random access memory store comprising at least one interconnect target port, that interconnect target port being connected to the first timeslot based interconnect; and 
 a peripheral, comprising:
 an interconnect target port; and 
 an interconnect master port connected to the first timeslot based interconnect; 
 
 in which that peripheral is adapted to issue memory transfer operations to the on-chip memory store over the peripheral's interconnect master port. 
 
     
     
         45 . A shared memory computing device as claimed in any one of  claims 35  to  44 , further comprising:
 a second timeslot based interconnect for transporting memory transfer requests and their corresponding responses; 
 an on-chip random access memory store comprising at least two interconnect target ports, in which:
 the first interconnect target port is connected to the first timeslot based interconnect; and 
 the second interconnect target port is connected to the second timeslot based interconnect; and 
 
 a peripheral, comprising:
 an interconnect-target; and 
 an interconnect-master port connected to the second timeslot based interconnect; 
 
 in which that peripheral is adapted to issue memory transfer operations to the on-chip memory store over the peripheral's interconnect master port. 
 
     
     
         46 . A process emulating a shared memory computing device as claimed in any one of  claims 35  to  45 . 
     
     
         47 . A process adapted to control a shared memory computing device as claimed in any one of  claims 35  to  45 . 
     
     
         48 . A signal carrying a representation in a hardware description language of a shared memory computing device as claimed in any one of  claims 35  to  45 . 
     
     
         49 . A machine readable substrate carrying a representation in a hardware description language of a shared memory computing device as claimed in any one of  claims 35  to  45 . 
     
     
         50 . A shared memory computing device comprising:
 M interconnect-nodes, where the value of M is at least 2, each interconnect-node comprising:
 an egress port; and 
 an ingress port; 
   a singular interconnect node comprising:
 an egress port; and 
 an ingress port; 
   a first M×1 interconnect for transporting memory transfer requests and their corresponding responses, comprising:
 M bidirectional ports, each comprising:
 an ingress port which is connected to the egress port of a different one of the M interconnect-nodes; and 
 an egress port, which is connected to the ingress port of a different one of the M interconnect-nodes; 
 
 a singular bidirectional port comprising:
 an egress port which is connected to the ingress port of the singular interconnect node; and 
 an ingress port which is connected to the egress port of the singular interconnect node; 
 
 a parallel-in, serial-out (PISO) M input port×1 output port shift register with M stages, in which:
 for each stage I of the M stages: that stage is connected to the egress port of the interconnect node I of M interconnect nodes; and 
 the output of stage I is connected to the egress port of the singular port of the interconnect; 
 
 a serial-in, parallel-out (SIPO) 1 input port×M output port module, in which the input is connected to the ingress port of the singular port of the interconnect; and 
 an arbiter and decoder module which is adapted to control the PISO M×1 shift register and the SIPO 1×M module. 
   
     
     
         51 . A shared memory computing device as claimed in  claim 50 , in which the M outputs of the SIPO 1×M module are released concurrently after receiving M inputs. 
     
     
         52 . A shared memory computing device as claimed in  claim 50  or  claim 51 , further comprising a second serial-in, parallel-out (SIPO) 1 input port×M output port module for transporting cache coherency traffic, in which:
 the input is connected to the egress port of the singular port of the interconnect; and 
 the arbiter and decoder module controls the second SIPO 1×M module. 
 
     
     
         53 . A shared memory computing device as claimed in any one of  claims 50  to  52 , in which the first M×1 timeslot based interconnect further comprises a means to enforce an access control policy. 
     
     
         54 . A shared memory computing device as claimed in any one of  claims 50  to  53  in which the interconnect node is an interconnect protocol transcoding bridge. 
     
     
         55 . A process emulating a shared memory computing device as claimed in any one of  claims 50  to  54 . 
     
     
         56 . A process adapted to control a shared memory computing device as claimed in any one of  claims 50  to  54 . 
     
     
         57 . A signal carrying a representation in a hardware description language of a shared memory computing device as claimed in any one of  claims 50  to  54 . 
     
     
         58 . A machine readable substrate carrying a representation in a hardware description language of a shared memory computing device as claimed in any one of  50  to  54 . 
     
     
         59 . A shared memory computing device comprising a combination of a shared memory computing device as claimed in any one or more of  claims 35  to  45 ; and a shared memory computing device as claimed in any one or more of one or more of  claims 50  to  54 . 
     
     
         60 . A shared memory computing device optimised for worst case execution time analysis comprising:
 N fully associative cache modules, where the value of N is at least 1, each fully associative cache module comprising:
 a master port: 
 a target port; 
 a means to track dirty cache-lines; 
 a finite state machine with one or more policies, in which at least one policy:
 employs an allocate on read strategy; 
 employs an allocate on write strategy; and 
 employs a least recently used eviction strategy; and 
 
   N processor cores, in which each core is assigned a different one of the N fully associative cache modules as its private cache.   
     
     
         61 . A shared memory computing device as claimed in  claim 60 , in which at least one of the N processor cores does not exhibit domino timing effects. 
     
     
         62 . A shared memory computing device as claimed in  claim 60  and  claim 61 , further comprising at least one interconnect master, in which the at least one of the N cache module can maintain cache coherency against memory transfer requests issued by that interconnect master. 
     
     
         63 . A shared memory computing device as claimed in  claim 62  in which the at least one cache module employs an update type of snooping. 
     
     
         64 . A shared memory computing device as claimed in any one of  claims 60  to  63 , in which at least one policy of the finite state machine of at least one of the N fully associative cache modules:
 employs an allocate on read strategy; 
 employs an allocate on write strategy; 
 employs a least recently used eviction strategy; and 
 in which a cache-line is solely evicted in response to servicing a memory transfer request which either:
 flushes at least one specific cache-line; or 
 requires the allocation of at least one cache-line. 
 
 
     
     
         65 . A shared memory computing device as claimed in any one of  claim 60  to  63 , in which at least one of the N fully associative cache modules further comprises a means to complete a memory transfer request which:
 is received on the target port of that cache module; and 
 results in a read-hit or write-hit while that cache module has one or more dirty cache-lines queued for eviction. 
 
     
     
         66 . A shared memory computing device as claimed in  claim 65 , in which:
 the at least one of the N fully associative cache modules further comprises a write buffer;   at least one policy of the finite state machine of the at least one of the N fully associative cache modules:
 employs an allocate on read strategy; 
 employs an allocate on write strategy; 
 employs a least recently used eviction strategy; and 
 in which:
 a cache-line is solely evicted in response to servicing a memory transfer request which either:
 flushes at least one specific cache-line; or 
 requires the allocation of at least one cache-line; and 
 
 those evicted cache-lines are queued in the write buffer of that cache module. 
 
   
     
     
         67 . A shared memory computing device as claimed in  claim 65 , in which at least one policy of the finite state machine of the at least one of the N fully associative cache modules:
 employs an allocate on read strategy;   employs an allocate on write strategy;   employs a least recently used eviction strategy; and   in which:
 each cache line is queued for eviction as soon as it becomes dirty; 
 writes can be performed to any dirty cache line which has been queued for eviction, but not yet evicted; and 
 a read-miss is serviced after all the currently outstanding dirty cache lines have been evicted. 
   
     
     
         68 . A shared memory computing device as claimed in  claim 65 , in which at least one policy of the finite state machine of the at least one of the N fully associative cache modules:
 employs an allocate on read strategy;   employs an allocate on write strategy;   employs a least recently used eviction strategy; and   in which:
 each cache line is queued for eviction as soon as it becomes dirty; 
 writes can be performed to any dirty cache-line which has been queued for eviction, but not yet evicted; and 
 a read-miss is serviced before all the currently outstanding dirty cache lines have been evicted. 
   
     
     
         69 . A shared memory computing device as claimed in  claim 65 , in which at least one policy of the finite state machine of the at least one of the N fully associative cache modules:
 employs an allocate on read strategy;   employs an allocate on write strategy;   employs a least recently used eviction strategy;   each cache line is queued for eviction as soon as it becomes dirty; and   in which:
 writes can be performed to any dirty cache line which has been queued for eviction, but not yet evicted; 
 a read-miss is serviced before the eviction of the currently outstanding dirty cache-lines queued for eviction on the condition that the execution time of each of the outstanding dirty-cache-lines evictions is not modified as a result of executing the read-miss operation first, otherwise the read-miss operation is delayed. 
   
     
     
         70 . A process emulating a shared memory computing device as claimed in any one of  claims 60  to  69 . 
     
     
         71 . A process adapted to control a shared memory computing device as claimed in any one of  claims 60  to  69 . 
     
     
         72 . A signal carrying a representation in a hardware description language of a shared memory computing device as claimed in any one of  claims 60  to  69 . 
     
     
         73 . A machine readable substrate carrying a representation in a hardware description language of a shared memory computing device as claimed in any one of  claims 60  to  69 . 
     
     
         74 . A shared memory computing device optimised for worst case execution time analysis comprising:
 at least one interconnect master,   N cache modules, where the value of N is at least 1, each cache module comprising:
 a master port; 
 a target port; and 
 a finite state machine that employs an update-type cache coherency policy; 
   N processor cores, in which each core:
 is assigned a different one of the N fully associative cache modules as its private cache; and 
   in which the execution time of memory transfer requests issued by each of the N processor cores is not modified by:
 the unrelated memory transfer requests issued by any of the other N processor cores; or 
 the unrelated memory transfer requests issued by at least one other interconnect master. 
   
     
     
         75 . A shared memory computing device as claimed in  claim 74 , in which the value of N is at least 2, and at least one of the N cache modules can maintain cache coherency against a different one of the N cache modules. 
     
     
         76 . A shared memory computing device as claimed in  claim 74  and  claim 75 , in which the at least one of the N cache modules can maintain cache coherency against memory transfer requests issued by the at least one interconnect master. 
     
     
         77 . A process emulating a shared memory computing device as claimed in any one of  claims 74  to  76 . 
     
     
         78 . A process adapted to control a shared memory computing device as claimed in any one of  claims 74  to  76 . 
     
     
         79 . A signal carrying a representation in a hardware description language of a shared memory computing device as claimed in any one of  claims 74  to  76 . 
     
     
         80 . A machine readable substrate carrying a representation in a hardware description language of a shared memory computing device as claimed in any one of  claims 74  to  76 . 
     
     
         81 . A bidirectional interconnect for transporting memory transfer requests and their corresponding memory transfer responses, comprising:
 a unidirectional interconnect to transport memory transfer requests; and   a unidirectional interconnect to transport memory transfer responses, adapted to transport memory transport responses that includes a copy of the corresponding memory transfer request.   
     
     
         82 . A process emulating a shared memory computing device as claimed in  claim 81 . 
     
     
         83 . A process adapted to control a shared memory computing device as claimed in  claim 81 . 
     
     
         84 . A signal carrying a representation in a hardware description language of a shared memory computing device as claimed in  claim 81 . 
     
     
         85 . A machine readable substrate carrying a representation in a hardware description language of a shared memory computing device as claimed in  claim 81 .