Memory system

Abstract

A memory system includes a semiconductor memory device that includes a plurality of memory cells, and a controller that controls an operation of the semiconductor memory device to set the memory cells to have a threshold voltage distribution corresponding to data being written therein, when data is being written in the memory cells, and to set the memory cells to have a neutral threshold voltage distribution, the neutral threshold voltage distribution being different from any of a plurality of threshold voltage distributions corresponding to valid data, when data is not being written in the memory cells.

What is claimed is: 
     
         1 . A memory system comprising:
 a semiconductor memory device that includes a plurality of memory cells; and   a controller that controls an operation of the semiconductor memory device to set the memory cells to have a threshold voltage distribution corresponding to data being written therein, when data is being written in the memory cells, and to set the memory cells to have a neutral threshold voltage distribution, the neutral threshold voltage distribution being different from any of a plurality of threshold voltage distributions corresponding to valid data, when data is not being written in the memory cells.   
     
     
         2 . The memory system according to  claim 1 , wherein the neutral threshold voltage distribution is substantially centered at a neutral threshold voltage. 
     
     
         3 . The memory system according to  claim 2 , wherein the neutral threshold voltage is 0. 
     
     
         4 . The memory system according to  claim 2 , wherein the neutral threshold voltage is between centers of two adjacent valid data threshold distributions. 
     
     
         5 . The memory system according to  claim 1 , wherein the neutral threshold voltage distribution overlaps parts of two valid data threshold distributions. 
     
     
         6 . The memory system according to  claim 1 , wherein the controller performs a normal erase operation using a first erase voltage when performing an erase operation of the memory cells and a weak erase operation using a second erase voltage, lower than the first erase voltage, in a process of setting the memory cells to have the neutral threshold voltage distribution. 
     
     
         7 . The memory system according to  claim 6 , wherein the process of setting the memory cells to have the neutral threshold voltage distribution further includes increasing threshold voltages of some of the memory cells. 
     
     
         8 . The memory system according to  claim 1 , wherein the controller performs a normal programming operation using a first programming voltage when performing a write operation on the memory cells and a weak programming operation using a second programming voltage, lower than the first programming voltage, in a process of setting the memory cells to have the neutral threshold voltage distribution. 
     
     
         9 . A memory system comprising:
 a semiconductor memory device that includes a plurality of blocks of memory cells, wherein each of the blocks is an erasure unit; and   a controller that controls an operation of the semiconductor memory device, wherein   during a write operation performed on a first group of memory cells of a block, the controller performs a first programming operation on the first group of memory cells so that the memory cells in the first group are set to have a threshold voltage distribution corresponding to data being written therein, and performs a second programming operation on a second group of memory cells of the block so that the memory cells in the second group are set to have a neutral threshold voltage distribution, the neutral threshold voltage distribution being different from any of a plurality of threshold voltage distributions corresponding to valid data.   
     
     
         10 . The memory system according to  claim 9 , wherein the neutral threshold voltage distribution is substantially centered at a neutral threshold voltage. 
     
     
         11 . The memory system according to  claim 10 , wherein the neutral threshold voltage is 0. 
     
     
         12 . The memory system according to  claim 10 , wherein the neutral threshold voltage is between centers of two adjacent valid data threshold distributions. 
     
     
         13 . The memory system according to  claim 9 , wherein the neutral threshold voltage distribution overlaps parts of two valid data threshold distributions. 
     
     
         14 . A method of preserving data retention characteristics of memory cells in a semiconductor memory device, comprising:
 checking a status of a block of memory cells;   determining that the block is an invalid data block or an erased block; and   setting the memory cells of the block to have a neutral threshold voltage distribution, the neutral threshold voltage distribution being different from any of a plurality of threshold voltage distributions corresponding to valid data.   
     
     
         15 . The method according to  claim 14 , wherein the neutral threshold voltage distribution is substantially centered at a neutral threshold voltage. 
     
     
         16 . The method according to  claim 15 , wherein the neutral threshold voltage is 0. 
     
     
         17 . The method according to  claim 15 , wherein the neutral threshold voltage is between centers of two adjacent valid data threshold distributions. 
     
     
         18 . The method according to  claim 14 , wherein the neutral threshold voltage distribution overlaps parts of two valid data threshold distributions. 
     
     
         19 . The method according to  claim 14 , wherein
 if the block is an invalid block, setting the memory cells of the block to have a neutral threshold voltage distribution by performing a weak erase operation on the memory cells using an erase voltage that is lower than an erase voltage used in a normal erase operation.   
     
     
         20 . The method according to  claim 14 , wherein
 if the block is an erased block, setting the memory cells of the block to have a neutral threshold voltage distribution by performing a weak programming operation on the memory cells using a programming voltage that is lower than a programming voltage used in a normal programming operation.