US2016261406A1PendingUtilityA1
Performing AES Encryption Or Decryption In Multiple Modes With A Single Instruction
Est. expiryMar 14, 2027(~0.6 yrs left)· nominal 20-yr term from priority
H04L 9/0631H04L 9/0637G06F 9/30007G06F 9/06G06F 21/00H04L 2209/12
51
PatentIndex Score
0
Cited by
0
References
0
Claims
Abstract
A machine-readable medium may have stored thereon an instruction, which when executed by a machine causes the machine to perform a method. The method may include combining a first operand of the instruction and a second operand of the instruction to produce a result. The result may be encrypted using a key in accordance with an Advanced Encryption Standard (AES) algorithm to produce an encrypted result. The method may also include placing the encrypted result in a location of the first operand of the instruction.
Claims
exact text as granted — not AI-modifiedWhat is claimed:
1 . A processor comprising:
a hardware decoder to decode instructions; a register file comprising a plurality of registers to store a plurality of blocks of data; and a hardware execution unit to execute decoded instructions decoded by the hardware decoder, the hardware execution unit including a crypto circuit to execute an Advanced Encryption Standard (AES) instruction that has at least two operands including a first operand and a second operand, the crypto circuit to encrypt the plurality of blocks of data according to a particular AES encryption mode, determine, during execution of the AES instruction, the particular AES encryption mode based at least in part on a value of the first operand, including to encrypt the second operand with a key stored in at least a first register of the register file prior to the AES instruction decoded by the hardware decoder and subsequently executed by the hardware execution unit, the at least first register an implicit register not specified by the AES instruction and included in the register file, wherein the crypto circuit is to execute the AES instruction according to the particular AES mode of Electronic Codebook (ECB) when the first operand value is zero for a plurality of iterations of a loop of hardware execution unit execution of the AES instruction as decoded by the hardware decoder for an AES instruction operation, and to execute the AES instruction according to the particular AES mode of Cipher Block Chaining (CBC) when the first operand value is an encrypted block of a prior iteration of the plurality of iterations of the loop of decoded AES instruction execution, wherein a number of the plurality of iterations of the loop of decoded AES instruction execution corresponds to a number of the plurality of blocks of data according to the particular AES encryption mode.Join the waitlist — get patent alerts
Track US2016261406A1 — get alerts on status changes and closely related new filings.
We store only your email — no account needed. See our privacy policy.