Microelectronic package with consolidated chip structures

Abstract

A chip package has multiple chips that may be arranged side-by-side or in a staggered, stair step arrangement. The contacts of the chips are connected to interconnect pads carried on the chips themselves or on a redistribution substrate. The interconnect pads desirably are arranged in a relatively narrow interconnect zone, such that the interconnect pads can be readily wire-bonded or otherwise connected to a package substrate.

1 . A microelectronic package comprising:
 (a) a package substrate having upper and lower surfaces and terminals at the lower surface;   (b) first and second chips disposed above the package substrate, each of the first and second chips having a front face, a rear face and contacts at the front face disposed in one or more columns extending in a column direction, the first and second chips being offset from one another by a center-to-center offset distance in a lateral direction transverse to the column direction;   (c) interconnect pads disposed in an elongated interconnect zone having a width less than the offset distance, the interconnect pads facing toward the package substrate at least some of the interconnect pads being electrically connected to at least some of the contacts of the first and second chips, at least some of the interconnect pads being electrically connected to at least some of the terminals of the package substrate.