Gallium nitride power devices

Abstract

Enhancement mode III-nitride devices are described. The 2DEG is depleted in the gate region so that the device is unable to conduct current when no bias is applied at the gate. Both gallium face and nitride face devices formed as enhancement mode devices.

What is claimed is: 
     
         1 . A method of forming a III-nitride device, comprising:
 forming a GaN material on a substrate;   forming a passivation layer over the GaN material, wherein the substrate, the GaN material, and the passivation layer are part of a structure having a first side adjacent the substrate and a second side opposite the substrate;   attaching a carrier wafer to the second side of the structure via a bonding layer provided therebetween; and   after attaching the carrier wafer to the second side of the structure, removing the substrate to expose a surface of the GaN material.   
     
     
         2 . The method of  claim 1 , wherein the GaN material comprises a GaN channel layer and an Al x GaN layer. 
     
     
         3 . The method of  claim 2 , wherein the Al x GaN layer has a thickness of less than 500 Angstroms. 
     
     
         4 . The method of  claim 2 , wherein the channel layer has a thickness of less than 300 Angstroms. 
     
     
         5 . The method of  claim 2 , wherein the GaN material further comprises a buffer layer between the substrate and the channel layer. 
     
     
         6 . The method of  claim 5 , wherein the buffer layer further comprises a sacrificial layer and an etch stop layer. 
     
     
         7 . The method of  claim 6 , wherein after removing the substrate, the sacrificial layer is selectively removed to expose a planar GaN surface. 
     
     
         8 . The method of  claim 1 , wherein the exposed planar GaN surface is an N-face of the GaN material. 
     
     
         9 . The method of  claim 1 , wherein III-nitride device is an enhancement mode transistor device. 
     
     
         10 . The method of  claim 1 , wherein the III-nitride device is configured to block at least 600V. 
     
     
         11 . A method of forming a III-nitride device, comprising:
 providing, on a substrate, a structure comprising a GaN material and a passivation layer formed on the GaN material, the GaN material contacting the substrate;   attaching a carrier wafer to a side of the structure opposite the substrate, wherein a bonding layer attaches the carrier wafer to the structure; and   after attaching the carrier wafer to the structure, removing the substrate to expose a surface of the GaN material.   
     
     
         12 . The method of  claim 11 , wherein the GaN material comprises a GaN channel layer and an Al x GaN layer. 
     
     
         13 . The method of  claim 12 , wherein the Al x GaN layer has a thickness of less than 500 Angstroms. 
     
     
         14 . The method of  claim 12 , wherein the channel layer has a thickness of less than 300 Angstroms. 
     
     
         15 . The method of  claim 12 , wherein the GaN material further comprises a buffer layer between the substrate and the channel layer. 
     
     
         16 . The method of  claim 15 , wherein the buffer layer further comprises a sacrificial layer and an etch stop layer. 
     
     
         17 . The method of  claim 16 , wherein after removing the substrate, the sacrificial layer is selectively removed to expose a planar GaN surface. 
     
     
         18 . The method of  claim 11 , wherein the exposed planar GaN surface is an N-face GaN material. 
     
     
         19 . The method of  claim 11 , wherein the III-nitride device is an enhancement mode transistor device. 
     
     
         20 . The method of  claim 10 , wherein the III-nitride device is configured to block at least 600V.