Controlled junction transistors and methods of fabrication

Abstract

Embodiments of the present invention provide transistors with controlled junctions and methods of fabrication. A dummy spacer is used during the majority of front end of line (FEOL) processing. Towards the end of the FEOL processing, the dummy spacers are removed and replaced with a final spacer material. Embodiments of the present invention allow the use of a very low-k material, which is highly thermally-sensitive, by depositing it late in the flow. Additionally, the position of the gate with respect to the doped regions is highly controllable, while dopant diffusion is minimized through reduced thermal budgets. This allows the creation of extremely abrupt junctions whose surface position is defined using a sacrificial spacer. This spacer is then removed prior to final gate deposition, allowing a fixed gate overlap that is defined by the spacer thickness and any diffusion of the dopant species.

What is claimed is: 
     
         1 .- 14 . (canceled) 
     
     
         15 . A semiconductor structure comprising:
 a semiconductor substrate;   two doped regions formed on a semiconductor channel disposed on the semiconductor substrate, having a gap between them;   a metal gate disposed on the semiconductor substrate over the gap, and extending over each of the two doped regions;   a plurality of spacers formed adjacent to the metal gate and in contact with one of the two doped regions; and   a cap region disposed on the metal gate.   
     
     
         16 . The semiconductor structure of  claim 15 , wherein the plurality of spacers are comprised of silicon nitride. 
     
     
         17 . The semiconductor structure of  claim 15 , wherein the plurality of spacers are comprised of SiBCN. 
     
     
         18 . The semiconductor structure of  claim 15 , wherein the metal gate extends over each doped region by a distance ranging from about 3 nanometers to about 10 nanometers. 
     
     
         19 . The semiconductor structure of  claim 15 , wherein each spacer of the plurality of spacers has a thickness ranging from about 3 nanometers to about 10 nanometers. 
     
     
         20 . The semiconductor structure of  claim 15 , wherein the metal gate includes at least one material selected from the group: tungsten, aluminum, titanium, hafnium oxide, silicon oxide, aluminum oxide, and zirconium oxide. 
     
     
         21 . The semiconductor structure of  claim 15 , further comprising a dielectric layer disposed over at least the two doped regions. 
     
     
         22 . A semiconductor structure comprising:
 a semiconductor substrate;   a metal gate disposed on the semiconductor substrate;   a first spacer in contact with the sides of the metal gate;   a plurality of second spacers, each in contact with the first spacer;   source/drain regions disposed on the semiconductor substrate, each in contact with one of the plurality of spacers;   a plurality of doped regions disposed in the semiconductor substrate, wherein each doped region is in contact with the first spacer.   
     
     
         23 . The semiconductor structure of  claim 22 , wherein the first spacer comprises silicon nitride, SiBCN, or SiOCN. 
     
     
         24 . The semiconductor structure of  claim 22 , wherein the metal gate includes at least one material selected from the group: tungsten, aluminum, titanium, hafnium oxide, silicon oxide, aluminum oxide, and zirconium oxide. 
     
     
         25 . The semiconductor structure of  claim 22 , further comprising a source/drain contact metal disposed over the source/drain regions. 
     
     
         26 . The semiconductor structure of  claim 25 , wherein the source/drain contact metal comprises tungsten. 
     
     
         27 . The semiconductor substrate of  claim 25 , further comprising a liner disposed between the source/drain contact metal and the source/drain regions. 
     
     
         28 . The semiconductor substrate of  claim 27 , wherein the liner comprises titanium nitride. 
     
     
         29 . The semiconductor substrate of  claim 22 , wherein the plurality of doped regions comprise arsenic, boron, antimony, or phosphorous.