Flexible command addressing for memory

Abstract

Flexible command addressing for memory. An embodiment of a memory device includes a dynamic random-access memory (DRAM); and a system element coupled with the DRAM, the system element including a memory controller for control of the DRAM. The DRAM includes a memory bank, a bus, the bus including a plurality of pins for the receipt of commands, and a logic, wherein the logic provides for shared operation of the bus for a first type of command and a second type of command received on a first set of pins.

1 . A memory device comprising:
 a dynamic random-access memory (DRAM); and   a system element coupled with the DRAM, the system element including a memory controller for control of the DRAM;   wherein the DRAM includes:
 a memory bank, 
 a bus, the bus including a plurality of pins for the receipt of commands, and 
 a logic, wherein the logic provides for shared operation of the bus for a first type of command and a second type of command received on a first set of pins. 
   
     
     
         2 . The memory device of  claim 1 , wherein the first type of command is a column command and the second type of command is a row command. 
     
     
         3 . The memory device of  claim 1 , wherein the logic is further to switch between a first mode providing for the shared operation of the bus and a second mode providing for separate bus operation for receipt of the first type of command on the first set of pins as dedicated pins and the second type of command on a second set of pins. 
     
     
         4 . The memory device of  claim 3 , wherein the first mode does not require inclusion of the second set of pins. 
     
     
         5 . The memory device of  claim 3 , further comprising a mode register for designation of the first mode or the second mode, the logic to switch to the first mode or the second mode based on a status of the mode register. 
     
     
         6 . The memory device of  claim 1 , wherein the DRAM is a first channel of a plurality of channels of the memory device. 
     
     
         7 . A method comprising:
 initializing a dynamic random-access memory (DRAM);   receiving a command for the DRAM, a command bus for the DRAM providing for shared operation for a first type of command and a second type of command, the bus having a first set of pins for the receipt of commands;   interpreting the command, wherein interpreting the command includes:
 upon determining that a set of bits of the command are in a first state, interpreting the command as the first type of command, and 
 upon determining that the set of bits of the command are in a second state, interpreting the command as the second type of command. 
   
     
     
         8 . The method of  claim 7 , wherein the first type of command is a column command and the second type of command is a row command. 
     
     
         9 . The method of  claim 7 , wherein interpreting the command further includes, upon determining that the set of bits of the command are in a third state, interpreting the command as a no operation (NOP) for both the first type of command and the second type of command. 
     
     
         10 . The method of  claim 7 , further comprising switching between a first mode providing for the shared operation of the bus and a second mode providing for separate bus operation for receipt of the first type command on the first set of pins as dedicated pins and the second type of command on a second set of pins. 
     
     
         11 . The method of  claim 10 , wherein switching between the first mode and the second mode includes switching to the first mode or the second mode based on a status of a mode register. 
     
     
         12 . The method of  claim 11 , wherein switching between the first mode and the second mode includes setting the mode register based on a received mode register set (MRS) command. 
     
     
         13 . The method of  claim 10 , further comprising defaulting to the first mode for the DRAM. 
     
     
         14 . A system comprising:
 a processor to process data for the system;   a transmitter, receiver, or both coupled with an omnidirectional antenna to transmit data, receive data, or both; and   a memory device for the storage of data, the memory device including:
 a dynamic random-access memory (DRAM); and 
 a system element coupled with the DRAM, the system element including a memory controller for control of the DRAM; 
   wherein the DRAM includes:
 a memory bank, 
 a bus, the bus including a plurality of pins for the receipt of commands, and 
 a logic, wherein the logic provides for shared operation of the bus for column commands and row commands received on a first set of pins. 
   
     
     
         15 . The system of  claim 14 , wherein the logic is further to switch between a first mode providing for the shared operation of the bus and a second mode providing for separate bus operation for receipt of one of either column or row commands on the first set of pins as dedicated pins and the other of column or row commands on a second set of pins. 
     
     
         16 . The system of  claim 15 , wherein the first mode does not require inclusion of the second set of pins. 
     
     
         17 . The system of  claim 15 , wherein the memory device further includes a mode register for designation of the first mode or the second mode, the logic to switch to the first mode or the second mode based on a status of the mode register. 
     
     
         18 - 22 . (canceled)