Non-uniform gate dielectric for u-shape mosfet

Abstract

A U-shaped gate dielectric structure is provided that has a horizontal gate dielectric portion having a vertical thickness, and a vertical gate dielectric wall portion extending upwards from the horizontal gate dielectric portion. The vertical gate dielectric wall portion has a lateral thickness that is greater than the vertical thickness of the horizontal gate dielectric portion. The U-shaped gate dielectric structure houses a gate conductor portion. Collectively, the U-shaped gate dielectric structure and the gate conductor portion provide a functional gate structure that has reduced capacitance.

1 . A semiconductor structure comprising:
 a functional gate structure located on a semiconductor material portion, wherein said functional gate structure comprises a U-shaped gate dielectric structure and a gate conductor portion, said U-shaped gate dielectric structure comprises a horizontal gate dielectric portion having a vertical thickness, and a vertical gate dielectric wall portion extending upwards from and surrounding exposed sidewalls of said horizontal gate dielectric portion, said vertical gate dielectric wall portion has a lateral thickness that is greater than said vertical thickness of said horizontal gate dielectric portion, and said gate conductor portion is located on said horizontal gate dielectric portion and within an area confined by said vertical gate dielectric wall portion; and   a source region located on one side of said functional gate structure and a drain region located on another side of the functional gate structure, wherein a source-side semiconductor material is positioned between said source region and a portion of said semiconductor material portion, and a drain-side semiconductor material is positioned between said drain region and another portion of said semiconductor material portion, said source region and said drain region each have a topmost surface that is located above a topmost surface of said semiconductor material portion and a topmost surface of said horizontal gate dielectric portion, and wherein each of said horizontal gate dielectric portion and said vertical gate dielectric wall portion has a bottommost surface that is coplanar with a bottommost surface of each of said source-side semiconductor material and said drain-side semiconductor material.   
     
     
         2 . The semiconductor structure of  claim 1 , wherein a sidewall edge of each of said source-side semiconductor material and said drain-side semiconductor materials contacts an outer sidewall of said vertical gate dielectric wall portion. 
     
     
         3 . The semiconductor structure of  claim 2 , wherein a portion of said semiconductor material portion directly beneath the functional gate structure provides a first channel region, and a portion of said source-side semiconductor material and a portion of said drain-side semiconductor material that contact said outer sidewall of said vertical gate dielectric wall portion provides a second channel region. 
     
     
         4 . The semiconductor structure of  claim 1 , further comprising a dielectric spacer located on said source-side semiconductor material and said drain-side semiconductor material, and positioned between said source region and said functional gate structure, and between said drain region and said functional gate structure. 
     
     
         5 . A semiconductor structure comprising:
 a functional gate structure located on a semiconductor material portion, wherein said functional gate structure comprises a U-shaped gate dielectric structure and a gate conductor portion, said U-shaped gate dielectric structure comprises a horizontal gate dielectric portion having a vertical thickness, and a vertical gate dielectric wall portion extending upwards from and surrounding exposed sidewalls of said horizontal gate dielectric portion, said vertical gate dielectric wall portion has a lateral thickness that is greater than said vertical thickness of said horizontal gate dielectric portion, and said gate conductor portion is located on said horizontal gate dielectric portion and within an area confined by said vertical gate dielectric wall portion; and   a source region located on one side of said functional gate structure and a drain region located on another side of the functional gate structure, wherein said source region and said drain region each have a topmost surface that is located above a topmost surface of said semiconductor material portion and a topmost surface of said horizontal gate dielectric portion, wherein said horizontal gate dielectric portion is present on a recessed channel region, said recessed channel region is located beneath a topmost surface of said semiconductor material portion.   
     
     
         6 . The semiconductor structure of  claim 5 , further comprising a source diffusion region located beneath said source region and within an upper portion of said semiconductor material portion, and a drain diffusion region located beneath said drain region and within an upper portion of said semiconductor material portion, wherein a sidewall edge of each of said source diffusion region and said drain diffusion region contacts an outer sidewall of said vertical gate dielectric wall portion. 
     
     
         7 . The semiconductor structure of  claim 5 , wherein a portion of said semiconductor material portion directly beneath the recessed channel region provides a first channel region, and vertical portions of said semiconductor material portion located on both sidewalls of said recessed channel region provide second channel regions. 
     
     
         8 . The semiconductor structure of  claim 5 , further comprising a dielectric material located on said source region and said drain region and surrounding said functional gate structure, wherein a topmost surface of said dielectric material is coplanar with a topmost surface of said U-shaped gate dielectric structure and a topmost surface of said gate conductor portion. 
     
     
         9 . The semiconductor structure of  claim 6 , further comprising a dielectric spacer located on said source diffusion region and said drain diffusion region, and positioned between said source region and said functional gate structure, and between said drain region and said functional gate structure. 
     
     
         10 . The semiconductor structure of  claim 5 , wherein said vertical gate dielectric wall portion comprises a combination of an outer vertical gate dielectric wall segment and an inner vertical gate dielectric segment. 
     
     
         11 . The semiconductor structure of  claim 1 , wherein said vertical gate dielectric wall portion has a topmost surface that is coplanar with a topmost surface of said gate conductor portion. 
     
     
         12 .- 20 . (canceled) 
     
     
         21 . The semiconductor structure of  claim 1 , wherein said functional gate structure contains a first channel region located directly beneath said U-shaped gate dielectric structure and within said semiconductor material portion, and a second channel region located in a portion of each of said source-side semiconductor material and said drain-side semiconductor material. 
     
     
         22 . The semiconductor structure of  claim 21 , wherein said first channel region has a first channel length and each second channel region has a second channel length. 
     
     
         23 . The semiconductor structure of  claim 22 , wherein a total gate length is equal to the first channel length+2(second channel length). 
     
     
         24 . The semiconductor structure of  claim 5 , wherein said vertical gate dielectric wall portion has a topmost surface that is coplanar with a topmost surface of said gate conductor portion. 
     
     
         25 . The semiconductor structure of  claim 5 , wherein said functional gate structure contains a first channel region located directly beneath said U-shaped gate dielectric structure and said recessed channel region and within said semiconductor material portion, and a second channel region located along a vertical portion of said semiconductor material portion that is located beneath each of said source region and said drain region. 
     
     
         26 . The semiconductor structure of  claim 25 , wherein said first channel region has a first channel length and each second channel region has a second channel length. 
     
     
         27 . The semiconductor structure of  claim 26 , wherein a total gate length is equal to the first channel length+2(second channel length). 
     
     
         28 . The semiconductor structure of  claim 5 , wherein a bottommost surface of each of said horizontal gate dielectric portion and said vertical gate dielectric wall portion is located beneath said topmost surface of said semiconductor material portion.