Memory devices including vertical pillars and methods of manufacturing and operating the same

Abstract

A semiconductor device includes a substrate of semiconductor material extending in a horizontal direction. A plurality of interlayer dielectric layers is provided on the substrate. A plurality of gate patterns are provided, each gate pattern being between a neighboring lower interlayer dielectric layer and a neighboring upper interlayer dielectric layer. A vertical channel of semiconductor material extends in a vertical direction through the plurality of interlayer dielectric layers and the plurality of gate patterns, a gate insulating layer between each gate pattern and the vertical channel that insulates the gate pattern from the vertical channel, the vertical channel being in contact with the substrate at a contact region that comprises a semiconducting region.

What is claimed is: 
     
         1 . A three dimensional NAND string device, comprising:
 a vertical channel of semiconductor material, at least one end portion of the vertical channel extending substantially perpendicular to a major surface of a substrate, wherein the vertical channel comprises a hollow body;   at least one of an air gap or an insulating material in the hollow body;   a plurality of control gates extending substantially parallel to the major surface of the substrate, wherein the plurality of control gates stacked vertically over the major surface of the substrate;   a blocking insulating layer in contact with the plurality of control gates;   a charge storage layer in contact with the blocking insulating layer; and   a tunnel insulating layer between the charge storage layer and the vertical channel.   
     
     
         2 . The device of  claim 1 , wherein:
 The vertical channel comprises a hollow cylinder shaped channel;   the tunnel insulating layer comprises a cylinder which surrounds the vertical channel;   the tunnel insulating layer comprises a single insulating layer;   the charge storage layer comprises a cylinder shaped charge storage layer which surrounds the tunnel insulating layer;   the blocking insulating layer comprises a cylinder which surrounds the charge storage layer;   the blocking insulating layer comprises a single insulating layer; and   the control gates surround the blocking insulating layer.   
     
     
         3 . The device of  claim 2 , wherein the substrate comprises a silicon substrate. 
     
     
         4 . The device of  claim 1 , wherein the air gap fills the entire hollow region of the vertical channel. 
     
     
         5 . The device of  claim 1 , further comprising an insulating air bridge layer located over the air gap and a doped semiconductor drain region located in electrical contact with an upper portion of the vertical channel layer over the insulating air bridge layer. 
     
     
         6 . The device of  claim 1 , further comprising a semiconductor drain air bridge layer located over the air gap. 
     
     
         7 . A method of making a three dimensional NAND string, comprising:
 forming a stack of alternating layers of a first material and a second material different from the first material over a substrate;   etching the stack to form at least one opening in the stack;   forming a blocking insulating layer in the at least one opening;   forming at least one charge storage layer in the at least one opening;   forming a tunnel insulating layer in the at least one opening; and   forming a hollow semiconductor channel layer having an air gap or an insulating material in the at least one opening.   
     
     
         8 . The method of  claim 7 , wherein:
 the at least one opening comprises a front side opening;   forming the blocking insulating layer comprises forming the blocking insulating layer in the front side opening;   forming the charge storage layer comprises forming the charge storage layer over the blocking insulating layer in the front side opening;   forming the tunnel insulating layer comprises forming the tunnel insulating layer over the charge storage layer in the front side opening; and   forming the hollow semiconductor channel layer comprises forming the semiconductor channel layer over the tunnel insulating layer in the front side opening.   
     
     
         9 . The method of  claim 7 , wherein the substrate comprises a silicon substrate. 
     
     
         10 . The method of  claim 7 , wherein the air gap fills the entire hollow region of the hollow semiconductor channel.