Semiconductor structure including a split gate nonvolatile memory cell and a high voltage transistor, and method for the formation thereof

Abstract

A semiconductor structure includes a split gate nonvolatile memory cell and a high voltage transistor. The nonvolatile memory cell includes an active region, a nonvolatile memory stack provided above the active region, a control gate electrode provided above the memory stack, a select gate electrode at least partially provided above the active region adjacent to the memory stack and a select gate insulation layer. The high voltage transistor includes an active region, a gate electrode and a gate insulation layer provided between the active region and the gate electrode. The select gate insulation layer of the nonvolatile memory device and the gate insulation layer of the high voltage transistor are at least partially formed of a same high-k dielectric material. The select gate electrode of the nonvolatile memory device and the gate electrode of the high voltage transistor are at least partially formed of a same metal.

What is claimed: 
     
         1 . A semiconductor structure, comprising:
 a split gate nonvolatile memory cell comprising an active region, a nonvolatile memory stack provided above said active region, a control gate electrode provided above said nonvolatile memory stack, a select gate electrode at least partially provided above said active region adjacent to said nonvolatile memory stack and a select gate insulation layer; and   a high voltage transistor comprising an active region, a gate electrode and a gate insulation layer provided between said active region and said gate electrode;   wherein said select gate insulation layer of said split gate nonvolatile memory cell and said gate insulation layer of said high voltage transistor are at least partially formed of a same high-k dielectric material; and   wherein said select gate electrode of said split gate nonvolatile memory cell and said gate electrode of said high voltage transistor are at least partially formed of a same metal.   
     
     
         2 . The semiconductor structure of  claim 1 , wherein said select gate insulation layer comprises a first portion arranged between said active region of said split gate nonvolatile memory cell and said select gate electrode and a second portion arranged between said select gate electrode and said control gate electrode. 
     
     
         3 . The semiconductor structure of  claim 2 , wherein each of said select gate insulation layer of said split gate nonvolatile memory cell and said gate insulation layer of said high voltage transistor comprises a first gate insulation layer arrangement comprising one or more sub-layers, wherein, for each of the sub-layers of said first gate insulation layer arrangement of said select gate insulation layer there is a corresponding sub-layer formed of a same material in said gate insulation layer of said high voltage transistor. 
     
     
         4 . The semiconductor structure of  claim 3 , wherein the corresponding sub-layers of said first gate insulation layer arrangements of said select gate insulation layer of said split gate nonvolatile memory cell and said gate insulation layer of said high voltage transistor are arranged in the same order. 
     
     
         5 . The semiconductor structure of  claim 4 , wherein the corresponding sub-layers of said first gate insulation layer arrangements of said select gate insulation layer of said split gate nonvolatile memory cell and said gate insulation layer of said high voltage transistor have substantially the same thickness. 
     
     
         6 . The semiconductor structure of  claim 5 , wherein said gate insulation layer of said high voltage transistor further comprises a layer of a dielectric material arranged between said first gate insulation layer arrangement and said active region of said high voltage transistor. 
     
     
         7 . The semiconductor structure of  claim 6 , wherein said layer of dielectric material arranged between said first gate insulation layer arrangement and said active region of said high voltage transistor is formed of silicon dioxide. 
     
     
         8 . The semiconductor structure of  claim 3 , further comprising a plurality of low voltage transistors, each of said plurality of low voltage transistors comprising an active region, a gate electrode provided above said active region and a gate insulation layer comprising a second gate insulation layer arrangement comprising one or more sub-layers, wherein, for each of said sub-layers, there is a corresponding sub-layer in said first gate insulation layer arrangements of said select gate insulation layer of said split gate nonvolatile memory cell and said gate insulation layer of said high voltage transistor, and wherein said gate electrodes of said low voltage transistors, said select gate electrode of said split gate nonvolatile memory cell and said gate electrode of said high voltage transistor are at least partially formed of the same material. 
     
     
         9 . The semiconductor structure of  claim 7 , wherein said plurality of low voltage transistors comprises a core transistor and an input/output transistor. 
     
     
         10 . The semiconductor structure of  claim 1 , wherein substantially no portion of said nonvolatile memory stack is provided between said select gate electrode and said control gate electrode. 
     
     
         11 . The semiconductor structure of  claim 10 , wherein said select gate electrode comprises a first portion provided adjacent to said control gate electrode and a second portion provided above said control gate electrode. 
     
     
         12 . A semiconductor structure, comprising:
 a split gate nonvolatile memory cell comprising an active region, a nonvolatile memory stack provided above said active region, a control gate electrode provided above said nonvolatile memory stack, a select gate electrode at least partially provided above said active region adjacent to said nonvolatile memory stack and a select gate insulation layer; and   a high voltage transistor comprising an active region, a gate electrode and a gate insulation layer provided between said active region and said gate electrode;   wherein said select gate insulation layer of said split gate nonvolatile memory cell and said gate insulation layer of said high voltage transistor are at least partially formed of a same high-k dielectric material, each of said select gate insulation layer of said split gate nonvolatile memory cell and said gate insulation layer of said high voltage transistor comprises a first gate insulation layer arrangement comprising one or more sub-layers, wherein, for each of said sub-layers of said first gate insulation layer arrangement of said select gate insulation layer there is a corresponding sub-layer formed of a same material in said gate insulation layer of said high voltage transistor, and wherein said gate insulation layer of said high voltage transistor further comprises a layer of a dielectric material arranged between said first gate insulation layer arrangement and said active region of said high voltage transistor; and   wherein said select gate electrode of said split gate nonvolatile memory cell and said gate electrode of said high voltage transistor are at least partially formed of a same metal.   
     
     
         13 . The semiconductor structure of  claim 12 , wherein said select gate insulation layer comprises a first portion arranged between said active region of said split gate nonvolatile memory cell and said select gate electrode and a second portion arranged between said select gate electrode and said control gate electrode. 
     
     
         14 . The semiconductor structure of  claim 12 , further comprising a plurality of low voltage transistors, each of said plurality of low voltage transistors comprising an active region, a gate electrode provided above said active region and a gate insulation layer comprising a second gate insulation layer arrangement comprising one or more sub-layers, wherein, for each of said sub-layers, there is a corresponding sub-layer in said first gate insulation layer arrangements of said select gate insulation layer of said split gate nonvolatile memory cell and said gate insulation layer of said high voltage transistor, and wherein said gate electrodes of said low voltage transistors, said select gate electrode of said split gate nonvolatile memory cell and said gate electrode of said high voltage transistor are at least partially formed of a same material. 
     
     
         15 . The semiconductor structure of  claim 14 , wherein said plurality of low voltage transistors comprise a core transistor and an input/output transistor. 
     
     
         16 . The semiconductor structure of  claim 12 , wherein substantially no portion of said nonvolatile memory stack is provided between said select gate electrode and said control gate electrode. 
     
     
         17 . The semiconductor structure of  claim 12 , wherein said layer of dielectric material arranged between said first gate insulation layer arrangement and said active region of said high voltage transistor is formed of silicon dioxide. 
     
     
         18 . The semiconductor structure of  claim 12 , wherein said select gate electrode comprises a first portion provided adjacent to said control gate electrode and a second portion provided above said control gate electrode.