Manufacturing method for semiconductor devices
Abstract
A manufacturing method for semiconductor devices includes the steps of forming an Ni/Au film that includes an Ni film and an Au film formed over the Ni film over a wiring that is coupled to each of a plurality of electrode pads formed over a principal surface of a semiconductor wafer and arranges each of the electrode pads at a different position, grinding a back surface of the semiconductor wafer, performing reduction treatment on a surface of the Ni/Au film, and forming a solder bump over the Ni/Au film. In the reduction treatment, respective processes of flux application, reflow soldering and cleaning are performed and the solder bump is bonded to the Ni/Au film after the reduction treatment has been completed. Thereby, bonding reliability in flip chip bonding of a semiconductor device is improved.
Claims
exact text as granted — not AI-modified1 - 12 . (canceled)
13 . A method for manufacturing a semiconductor device, comprising:
(a) providing a semiconductor substrate having a multilayer wiring and an electrode pad formed at an uppermost layer of the multilayer wiring; (b) after (a), forming a rewiring electrically coupled to the electrode pad; (c) after (b), forming a first metal film over the rewiring; (d) after (c), forming a second metal film over the first metal film; (e) after (d), performing a reduction treatment on a surface of the second metal film; and (f) after (e), forming a bump over the second metal film.
14 . The method for manufacturing a semiconductor device according to claim 13 , wherein the first metal film is a Ni film.
15 . The method for manufacturing a semiconductor device according to claim 14 , wherein the second metal film is an Au film.
16 . The method for manufacturing a semiconductor device according to claim 13 , wherein the bump is an Sn bump.
17 . The method for manufacturing a semiconductor device according to claim 14 , wherein (e) comprises:
(e1) applying a flux constituent material; (e2) after (e1), performing reflow soldering; and (e3) after (e2), performing cleaning.
18 . The method for manufacturing a semiconductor device according to claim 17 , wherein the flux constituent material is a same material as that of a flux material that is applied to the second metal film after the reduction treatment has been performed and before the bump is formed.
19 . The method for manufacturing a semiconductor device according to claim 18 , wherein before (f), a back surface that is opposite to a principal surface of the semiconductor substrate is ground.
20 . The method for manufacturing a semiconductor device according to claim 13 , further comprising:
grinding a back surface of the semiconductor substrate, the back surface being opposite to a principal surface of the semiconductor substrate, the multilayer wiring being formed over the principal surface.
21 . The method for manufacturing a semiconductor device according to claim 13 , wherein the reduction treatment comprises acid cleaning.
22 . The method for manufacturing a semiconductor device according to claim 13 , wherein the forming the second metal film in (d) includes electroless plating.
23 . A method for manufacturing a semiconductor device, comprising:
forming a first metal film over a rewiring on a semiconductor substrate, the semiconductor substrate having a multilayer wiring and an electrode pad formed at an upper layer of the multilayer wiring, the rewiring being electrically connected to the electrode pad; forming a second metal film over the first metal film; performing a reduction treatment on a surface of the second metal film; and forming a bump over the second metal film after the reduction treatment.
24 . The method of claim 23 , wherein the first metal film comprises Ni.
25 . The method of claim 23 , wherein the second metal film comprises Au.
26 . The method of claim 23 , wherein the bump comprises Sn.
27 . The method of claim 23 , wherein the performing the reduction treatment comprises applying a flux constituent material followed by reflow soldering and cleaning.Join the waitlist — get patent alerts
Track US2016247772A1 — get alerts on status changes and closely related new filings.
We store only your email — no account needed. See our privacy policy.