Methods and devices for determining logical to physical mapping on an integrated circuit

Abstract

Devices for mapping logical addresses to physical locations on an integrated circuit die are disclosed herein. An embodiment includes a die which has a plurality of bits that are electrically accessible by way of logical addresses. A plurality of bits have intentionally induced defects that form a predetermined fault pattern.

What is claimed is: 
     
         1 - 10 . (canceled) 
     
     
         11 . A die comprising:
 a plurality of bits, each of the bits being accessible by a logical address; and   a plurality of the bits having intentionally induced defects, wherein the plurality of defective bits form a predetermined fault pattern.   
     
     
         12 . The die of  claim 11 , wherein the bits comprise at least one component and wherein the intentionally induced defects are caused by at least one known defect in the at least one component. 
     
     
         13 . The die of  claim 11 , wherein the die comprises two conducting layers electrically connected by way of vias, wherein each of the plurality of bits has components that are electrically connected to a via, and wherein the intentionally induced defects are vias that do not electrically conduct. 
     
     
         14 . The die of  claim 11 , wherein the predetermined fault pattern includes a first line that is intersected by at least one second line. 
     
     
         15 . The die of  claim 14 , wherein at least one second line is substantially perpendicular to the first line. 
     
     
         16 . The die of  claim 11 , wherein the predetermined fault pattern includes a first line that is intersected by a plurality of second lines. 
     
     
         17 . The die of  claim 11  wherein the predetermined fault pattern includes at least one square. 
     
     
         18 - 20 . (canceled) 
     
     
         21 . The die of  claim 11 , wherein the predetermined fault pattern is induced by a reticle. 
     
     
         22 . The die of  claim 11 , wherein the intentionally induced deflects are induced in a plurality of dielectric layers. 
     
     
         23 . The die of  claim 11 , wherein the intentionally induced deflects are induced in a plurality of metal layers. 
     
     
         24 . The die of  claim 21 , wherein the reticle makes vias in the bits of the fault pattern defective. 
     
     
         25 . The die of  claim 15 , wherein the predetermined fault pattern is in a shape of an F.