High-Frequency Switching Circuit

Abstract

A high-frequency switching circuit includes a high-frequency switching transistor, wherein a high-frequency signal-path extends via a channel-path of the high-frequency switching transistor. The high-frequency switching circuit includes a control circuit and the control circuit is configured to apply at least two different bias potentials to a substrate of the high-frequency switching transistor, depending on a control signal received by the control circuit.

What is claimed is: 
     
         1 . A high-frequency switching circuit comprising:
 a first high-frequency switching transistor comprising a first channel terminal and a second channel terminal;   a second high-frequency switching transistor comprising a first channel terminal coupled to the second channel terminal of the first high-frequency switching transistor and a second channel terminal coupled to a potential node;   a first channel resistor coupled between the second channel terminal of the first high-frequency switching transistor and a potential node;   a first switch coupled between the potential node and a reference voltage node; and   a controller configured to
 turn-off the first switch when the first high-frequency switching transistor and the second high-frequency switching transistor are turned-on, wherein the potential node is left floating, and 
 turn-on the first switch when the first high-frequency switching transistor and the second high-frequency switching transistor are turned-off. 
   
     
     
         2 . The high-frequency switching circuit of  claim 1 , wherein the first switch comprises:
 a third high-frequency switching transistor having a first channel terminal coupled to the potential node;   a fourth high-frequency switching transistor having a first terminal coupled to a second terminal of the third high-frequency switching transistor and a second terminal coupled to the reference voltage node; and   a second channel resistor coupled between the second channel terminal of the third high-frequency switching transistor and the potential node, wherein the controller is further configured to
 turn-on the first switch by turning-on the third high-frequency switching transistor and the fourth high-frequency switching transistor, and 
 turn-off the first switch by turning-off the third high-frequency switching transistor and the fourth high-frequency switching transistor. 
   
     
     
         3 . The high-frequency switching circuit of  claim 2 , further comprising:
 a first gate resistor coupled between a gate of the first high-frequency switching transistor and a first switch state signal line;   a second gate resistor coupled between a gate of the second high-frequency switching transistor and the first switch state signal line;   a third gate resistor coupled between a gate of the third high-frequency switching transistor and a second switch state signal line; and   a fourth gate resistor coupled between a gate of the fourth high-frequency switching transistor and the second switch state signal line.   
     
     
         4 . The high-frequency switching circuit of  claim 3 , wherein a potential of the first switch state signal line is inverted with respect to a potential of the second switch state signal line. 
     
     
         5 . The high-frequency switching circuit according to  claim 3 , wherein resistances of the first channel resistor and the second channel resistor are greater than resistances of the first gate resistor, second gate resistor, third gate resistor and fourth gate resistor. 
     
     
         6 . The high-frequency switching circuit of  claim 1 , wherein a potential of the reference voltage node is chosen such channel regions of the first high-frequency switching transistor and second high-frequency switching transistor are depleted when the first switch is turned-on. 
     
     
         7 . The high-frequency switching circuit of  claim 1 , wherein a potential of the reference voltage node comprises a ground potential. 
     
     
         8 . The high-frequency switching circuit of  claim 1 , wherein the first high-frequency switching transistor and the second high-frequency switching transistor form a high-frequency switch having a first switch terminal coupled to the first channel terminal of the first high-frequency switching transistor and a second switch terminal coupled to the second channel terminal of the second high-frequency switching transistor. 
     
     
         9 . The high-frequency switching circuit of  claim 8 , wherein the first switch terminal of the high-frequency switch is coupled to an antenna network. 
     
     
         10 . The high-frequency switching circuit of  claim 1 , wherein the first high-frequency switching transistor and the second high-frequency switching transistor are NMOS transistors. 
     
     
         11 . A high-frequency switching circuit comprising:
 a first high-frequency switching transistor comprising a first channel terminal and a second channel terminal;   a second high-frequency switching transistor comprising a first channel terminal coupled to the second channel terminal of the first high-frequency switching transistor and a second channel terminal coupled to a potential node;   a first channel resistor coupled between the second channel terminal of the first high-frequency switching transistor and a potential node;   a third high-frequency switching transistor having a first channel terminal coupled to the potential node;   a fourth high-frequency switching transistor having a first terminal coupled to a second terminal of the third high-frequency switching transistor and a second terminal coupled to a reference voltage node;   a second channel resistor coupled between the second channel terminal of the third high-frequency switching transistor and the potential node; and   a controller configured to
 turn-on the first high-frequency switching transistor and the second high-frequency switching transistor and turn-off the third high-frequency switching transistor and the fourth high-frequency switching transistor in a first state; and 
 turn-off the first high-frequency switching transistor and the second high-frequency switching transistor and turn-on the third high-frequency switching transistor and the fourth high-frequency switching transistor in a first state, wherein the potential node is left floating in the first state. 
   
     
     
         12 . The high-frequency switching circuit of  claim 11 , wherein:
 the controller comprises
 a first switch state output coupled to a gate of the first high-frequency switching transistor and to a gate of the second high-frequency switching transistor, and 
 a second switch state output coupled to a gate of the third high-frequency switching transistor and to a gate of the third high-frequency switching transistor; and 
   the controller is further configured to turn-on and turn-off the first high-frequency switching transistor and the second high-frequency switching transistor via the first switch state output, and turn-on and turn-off the third high-frequency switching transistor and the fourth high-frequency switching transistor via the second switch state output.   
     
     
         13 . The high-frequency switching circuit of  claim 12 , further comprising:
 a first gate resistor coupled between a gate of the first high-frequency switching transistor and a first switch state output;   a second gate resistor coupled between a gate of the second high-frequency switching transistor and the first switch state output;   a third gate resistor coupled between a gate of the third high-frequency switching transistor and a second switch state output; and   a fourth gate resistor coupled between a gate of the fourth high-frequency switching transistor and the second switch state output.   
     
     
         14 . The high-frequency switching circuit according to  claim 13 , wherein resistances of the first channel resistor and the second channel resistor are greater than resistances of the first gate resistor, second gate resistor, third gate resistor and fourth gate resistor. 
     
     
         15 . The high-frequency switching circuit of  claim 11 , wherein a potential of the reference voltage node is chosen such channel regions of the first high-frequency switching transistor and second high-frequency switching transistor are depleted when the third high-frequency switching transistor and the fourth high-frequency switching transistor are turned-on. 
     
     
         16 . The high-frequency switching circuit of  claim 15 , wherein a potential of the reference voltage node comprises a ground potential. 
     
     
         17 . A method of operating a high-frequency switching circuit comprising a first high-frequency switching transistor, a second high-frequency switching transistor comprising a first channel terminal coupled to a first channel terminal of the first high-frequency switching transistor and a second channel terminal coupled to a potential node, a first channel resistor coupled between the first channel terminal of the first high-frequency switching transistor and a potential node, and a first switch coupled between the potential node and a reference voltage node, the method comprising:
 in a first state, turning-on the first high-frequency switching transistor and the second high-frequency switching transistor and turning-off the first switch, wherein the potential node is left floating in the first state; and   in a second state, turning-off the first high-frequency switching transistor and the second high-frequency switching transistor and turning-on the first switch.   
     
     
         18 . The method of  claim 17 , further comprising:
 applying a high-frequency signal to a second terminal of the first high-frequency switching transistor; and   monitoring the high-frequency signal at the second terminal of the second high-frequency switching transistor.   
     
     
         19 . The method of  claim 18 , wherein:
 applying the high-frequency signal comprises applying the high-frequency signal via an antenna; and   monitoring the high-frequency signal comprises monitoring the high-frequency signal using a receiver.   
     
     
         20 . The method of  claim 17 , further comprising applying a reference potential at the reference voltage node, wherein the applied reference potential depletes channel regions of the first and second high-frequency switching transistors when the first switch is turned-on.