Method for manufacturing semiconductor device with recess, epitaxial growth and diffusion

Abstract

A semiconductor device including a gate electrode disposed on a semiconductor substrate and source/drain regions disposed at both sides of the gate electrode, the source/drain regions being formed by implanting impurities. The source/drain regions include an epitaxial layer formed by epitaxially growing a semiconductor material having a different lattice constant from that of the semiconductor substrate in a recessed position at a side of the gate electrode, and a diffusion layer disposed in a surface layer of the semiconductor substrate.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a substrate;   a gate electrode on the substrate;   a diffusion region comprising impurities in a surface portion of the substrate; and   an epitaxial region having a lattice constant different from a lattice constant of the substrate, the epitaxial region being between the gate electrode and the diffusion region along a channel length direction of the semiconductor device,   wherein,
 a source/drain region includes the epitaxial region and the diffusion region, and 
 a depth of the diffusion region within the substrate is greater than a depth of the epitaxial region within the substrate. 
   
     
     
         2 . The semiconductor device of  claim 1 , wherein the gate electrode forms a part of a p-type transistor. 
     
     
         3 . The semiconductor device of  claim 1 , further comprising an element isolation layer in the substrate, the element isolation layer comprising an insulating material, wherein, the diffusion region is between the epitaxial region and the element isolation layer along the channel length direction. 
     
     
         4 . The semiconductor device of  claim 3 , wherein the element isolation layer and the epitaxial region do not contact each other. 
     
     
         5 . The semiconductor device of  claim 1 , wherein the epitaxial region comprises a substantially hexagonal shape in cross sectional view. 
     
     
         6 . The semiconductor device of  claim 1 , wherein a height of the epitaxial region is higher than a height of the diffusion region with respect to a surface of the substrate. 
     
     
         7 . The semiconductor device of  claim 1 , further comprising a silicide layer in contact with the epitaxial region. 
     
     
         8 . The semiconductor device of  claim 1 , further comprising a silicide layer in contact with the diffusion region. 
     
     
         9 . The semiconductor device of  claim 1 , wherein:
 a first transistor includes at least the gate electrode and the epitaxial region,   a second transistor includes at least another gate electrode and another epitaxial region, and   the diffusion region is between the epitaxial region of the first transistor and the another epitaxial region of the second transistor.   
     
     
         10 . The semiconductor device of  claim 1 , wherein a cross section of the epitaxial region has a convex polygonal shape. 
     
     
         11 . The semiconductor device of  claim 1 , wherein the epitaxial region occupies at least a majority of a space within the recess portion. 
     
     
         12 . The semiconductor device of  claim 1 , further comprising a stress film over the epitaxial region and the gate electrode. 
     
     
         13 . The semiconductor device of  claim 12 , wherein the stress film comprises silicon nitride. 
     
     
         14 . The semiconductor device of  claim 1 , further comprising a silicide layer on the epitaxial region and a contact disposed on the silicide layer. 
     
     
         15 . The semiconductor device of  claim 15 , wherein the contact includes at least tungsten. 
     
     
         16 . The semiconductor device of  claim 15 , wherein the contact includes titanium as a barrier film. 
     
     
         17 . The semiconductor device of  claim 15 , wherein:
 the contact includes a tungsten film, and   a thickness of the tungsten film is in a range of 100 nm to 500 nm.   
     
     
         18 . A semiconductor device comprising:
 a substrate;   a gate electrode on the substrate;   a diffusion region comprising impurities in a surface portion of the substrate;   an epitaxial region comprising a semiconductor material having a lattice constant different from a lattice constant of the substrate, the epitaxial region being between the gate electrode and the diffusion region along a channel length direction of the semiconductor device;   an element isolation layer in the substrate, the element isolation layer comprising an insulating material, and   wherein,
 a source/drain region includes the epitaxial region and the diffusion region, 
 the diffusion region is between the epitaxial region and the element isolation layer along the channel length direction of the semiconductor substrate, and 
 the element isolation layer and the epitaxial region do not contact each other. 
   
     
     
         19 . The semiconductor device of  claim 18 , wherein a depth of the diffusion region within the substrate is greater than a depth of the epitaxial region within the substrate. 
     
     
         20 . The semiconductor device of  claim 18 , wherein a height of the epitaxial region is higher than a height of the diffusion region with respect to a surface of the substrate.