Power integrated devices, electronic devices including the same, and electronic systems including the same

Abstract

A power integrated device includes a semiconductor layer having first conductivity, a source region and a drain region each having second conductivity and disposed in the semiconductor layer, wherein the source region and the drain region are spaced apart from each other, a first drift region having the second conductivity, disposed in the semiconductor layer, and surrounding the drain region, a second drift region having the second conductivity, disposed in the semiconductor layer, contacting a sidewall of the first drift region, and having an impurity concentration lower than an impurity concentration of the first drift region, a gate insulation layer disposed over a channel region between the source region and the second drift region and extending over the second drift region, a field insulation plate disposed over the second drift region and the first drift region, contacting a sidewall of the gate insulation layer, and having a planar structure, and a gate conductive pattern disposed over the gate insulation layer, wherein the gate conductive pattern extends over the field insulation plate.

What is claimed is: 
     
         1 . A power integrated device comprising:
 a semiconductor layer having first conductivity;   a source region and a drain region each having second conductivity and disposed in the semiconductor layer, wherein the source region and the drain region are spaced apart from each other;   a first, drift region having the second conductivity, disposed in the semiconductor layer, and surrounding the drain region;   a second drift region having the second conductivity, disposed in the semiconductor layer, contacting a sidewall of the first drift region, and having an impurity concentration lower than an impurity concentration of the first drift region;   a gate insulation layer disposed over a channel region between the source region and the second drift region and extending over the second drift region;   a field insulation plate disposed over the second drift region and the first drift region, contacting a sidewall of the gate insulation layer, and having a planar structure; and   a gate conductive pattern disposed over the gate insulation layer,   wherein the gate conductive pattern extends over the field insulation plate.   
     
     
         2 . The power integrated device of  claim 1 , further comprising:
 a body region having the first conductivity, disposed in the semiconductor layer, surrounding the source region, and spaced apart from the second drift region.   
     
     
         3 . The power integrated device of  claim 2 , wherein the body region has a junction depth which is less than a junction depth of the first drift region and greater than a junction depth of the second drift region. 
     
     
         4 . The power integrated device of  claim 1 , wherein an impurity concentration of the second drift region is within the range of about 40% to about 70% of an impurity concentration of the first drift region. 
     
     
         5 . The power integrated device of  claim 1 , wherein an impurity concentration in the second drift region gradually reduces from an interface between the first and second drift regions toward the opposite side of the interface. 
     
     
         6 . The power integrated device of  claim 1 , wherein the first drift region is spaced apart from an interface between the gate insulation layer and the field insulation plate. 
     
     
         7 . The power integrated device of  claim 6 , wherein a distance from the first drift region to the interface between the gate insulation layer and the field insulation plate is substantially equal to or greater than a distance from the channel region to the interface between the gate insulation layer and the field insulation plate. 
     
     
         8 . The power integrated device of  claim 1 , wherein a bottom surface of the field insulation plate is located substantially at the same level as a top surface of the first drift region and a top surface of the second drift region. 
     
     
         9 . The power integrated device of  claim 1 , wherein a sidewall of the field insulation plate is in contact with a sidewall of the gate insulation layer and another sidewall of the field insulation plate opposite to gate insulation layer is aligned with a sidewall of the drain region. 
     
     
         10 . The power integrated device of claim wherein the field insulation plate includes an oxide layer. 
     
     
         11 . A power integrated device comprising:
 a semiconductor layer having first conductivity;   a source region having second conductivity;   drift region having the second conductivity, disposed in the semiconductor layer, and spaced apart from the source region by a channel region;   a drain region having the second conductivity and disposed in an upper portion of the drift region;   a gate insulation layer disposed over the channel region and extending over the drift region;   a first field insulation plate disposed over the drift region, contacting a side II of the gate insulation layer, and having a planar structure;   a second field insulation plate extending from under the first field insulation plate into the drift region and having a trench structure; and   a gate conductive pattern disposed over the gate insulation layer,   wherein the gate conductive pattern extends over the first field insulation plate.   
     
     
         12 . The power integrated device of  claim 11 , wherein the drift region includes:
 a first drift region having the second conductivity, disposed in the semiconductor layer, and surrounding the drain region; and   a second drift region having the second conductivity and disposed in the semiconductor layer between the channel region and the first drift region,   wherein the second drift region contacts a sidewall of the first drift region and has an impurity concentration lower than an impurity concentration of the first drift region.   
     
     
         13 . The power integrated device of  claim 12 , wherein a junction depth of the first drift region is greater than a junction depth of the second drift region. 
     
     
         14 . The power integrated device of  claim 12 , wherein the impurity concentration of the second drift region is within the range of about 40% to about 70% of the impurity concentration of the first drift region. 
     
     
         15 . The power integrated device of  claim 14 , wherein the impurity concentration of the second drift region gradually reduces from an interface between the first and second drift regions toward the opposite side of the interface. 
     
     
         16 . The power integrated device of  claim 14 , wherein an interface between the gate insulation layer and the first field insulation plate is disposed over the second drift region. 
     
     
         17 . The power integrated device of  claim 14 , further comprising;
 a body region having the first conductivity, disposed in the semiconductor layer, surrounding the source region, and spaced apart from the second drift region.   
     
     
         18 . The power integrated device of  claim 14 , further comprising:
 a first buried layer having the second conductivity and disposed in the semiconductor layer; and   a second buried layer having the first conductivity, disposed between the first buried layer and the first drift region.   
     
     
         19 . The power integrated device of  claim 18 , wherein a top surface and a bottom surface of the second buried layer are in contact with a bottom surface of the first drift region and a top surface of the first buried layer, respectively. 
     
     
         20 . The power integrated device of  claim 11 ,
 wherein a first region of the second field insulation plate overlapping with the first field insulation plate has a first length when measured in a first direction which extends from the source region toward the drain region,   wherein a second region of the second field insulation plate not overlapping with the first field insulation plate has a second length when measured in the first direction, and   wherein the first length is substantially equal to or greater than the second length.   
     
     
         21 . The power integrated device of  claim 11 , wherein a bottom surface of the first field insulation plate is located substantially at the same level as a top surface of the drift region and a top surface of the second field insulation plate. 
     
     
         22 . The power integrated device of  claim 11 , wherein each of the first and the second field insulation plates includes an oxide layer.