Semiconductor devices and methods for manufacturing the same

Abstract

Semiconductor devices and methods for manufacturing the same are provided. An example method may include: forming a sacrificial gate stack on a substrate; forming a gate spacer on sidewalls of the sacrificial gate stack; forming an interlayer dielectric layer on the substrate and planarizing it to expose the sacrificial gate stack; partially etching back the sacrificial gate stack to form an opening; expanding the resultant opening so that the opening is in a shape whose size gradually increases from a side adjacent to the substrate towards an opposite side away from the substrate; and removing a remaining portion of the sacrificial gate stack and forming a gate stack in a space defined by the gate spacer.

1 . A method for manufacturing a semiconductor device, comprising:
 forming a sacrificial gate stack on a substrate;   forming a gate spacer on sidewalls of the sacrificial gate stack;   forming an interlayer dielectric layer on the substrate and planarizing it to expose the sacrificial gate stack;   partially etching back the sacrificial gate stack to form an opening;   expanding the opening so that the opening is in a shape whose size gradually increases from a side adjacent to the substrate towards an opposite side away from the substrate; and   removing a remaining portion of the sacrificial gate stack and forming a gate stack in a space defined by the gate spacer.   
     
     
         2 . The method according to  claim 1 , wherein the expanding comprises performing atom and/or ion bombardment. 
     
     
         3 . The method according to  claim 2 , wherein the atom and/or ion bombardment comprises plasma sputtering. 
     
     
         4 . The method according to  claim 1 , wherein the expanded opening is self-aligned to the remaining portion of the sacrificial gate stack. 
     
     
         5 . The method according to  claim 1 , wherein the gate stack comprises a gate dielectric layer and a gate conductor layer, and wherein the method further comprises:
 partially etching back the gate conductor layer;   forming an dielectric layer on the gate conductor layer to cover the etched back gate conductor layer.   
     
     
         6 . A semiconductor device, comprising:
 a substrate;   a gate stack formed on the substrate and a gate spacer on sidewalls of the gate stack,   wherein a volume defined by the gate spacer is in a shape whose size gradually increases from a side adjacent to the substrate towards an opposite side away from the substrate at least in a portion of the volume on the side away from the substrate.   
     
     
         7 . The semiconductor device according to  claim 6 , wherein the gate stack comprises a gate dielectric layer and a gate conductor layer, wherein the gate conductor layer is recessed with respect to an end of the gate spacer on the side away from the substrate, and the semiconductor device further comprises a dielectric layer covering the gate conductor layer. 
     
     
         8 . The semiconductor device according to  claim 6 , further comprising a fin formed on the substrate, wherein the gate stack intersects with the fin. 
     
     
         9 . The semiconductor device according to  claim 8 , further comprising a punch through stopper formed in a region beneath a portion of the fin intersecting with the gate stack.