Package structure and its fabrication method

Abstract

This disclosure provides a package structure and its fabrication method. The package structure includes: a protective insulation layer; a wiring layer including at least one metal wire and disposed on the protective insulation layer; and a first package unit disposed on the wiring layer and including a plurality of metal pillars, a first integrated-circuit chip and a first molding compound layer; wherein the plural metal pillars are located in a pillar region and electrically connected to the at least one metal wire, the first integrated-circuit chip is located in a device region and electrically connected to the at least one metal wire, and the first molding compound layer filling up the remaining part of the first package unit.

What is claimed is: 
     
         1 . A method for fabricating a package structure, comprising the steps of:
 (A) providing a carrier;   (B) forming a wiring layer on the carrier while enabling the wiring layer to be formed including at least one metal wire;   (C) forming a plurality of metal pillars on the wiring layer while enabling the plural metal pillars to connect electrically to the at least one metal wire;   (D) providing a first integrated-circuit chip to be disposed on the wiring layer while enabling the first integrated-circuit chip to connect electrically to the at least one metal wire without overlapping with the plural metal pillars;   (E) forming a first molding compound layer on the carrier while enabling the first molding compound layer to cover all the wiring layer, the plural metal pillars and the first integrated-circuit chip;   (F) removing a portion of the first molding compound layer for exposing the plural metal pillars;   (G) providing a second integrated-circuit chip to be disposed on the first molding compound layer while enabling the second integrated-circuit chip to connect electrically to the plural metal pillars;   (H) forming a second molding compound layer on the first molding compound layer while enabling the second molding compound layer to cover the second integrated-circuit chip; and   (I) removing the carrier and forming a protective insulation layer under the wiring layer.   
     
     
         2 . The method of  claim 1 , wherein the forming of a wiring layer in the step (B) further comprises the steps of:
 forming and patterning a first photo resist layer on the carrier;   forming a first metal layer on an opening region of the patterned first photoresist layer; and   patterning the first metal layer by the removing of the first photoresist layer so as to form the at least one metal wire.   
     
     
         3 . The method of  claim 1 , wherein the forming of a wiring layer in the step (B) further comprises the steps of:
 forming a dielectric material layer on the carrier;   removing a portion of the dielectric material layer into a pattern of the at least one metal wire accordingly; and   forming a first metal layer on the region of the carrier where the dielectric material layer had been removed so as to form the at least one metal wire.   
     
     
         4 . The method of  claim 1 , wherein the forming of a wiring layer in the step (B) further comprises the steps of:
 forming a first metal layer on the carrier;   removing a portion of the first metal layer into a pattern of the at least one metal wire accordingly; and   disposing a dielectric material layer on the region of the carrier where the first metal layer had been removed so as to enable the dielectric material layer along with the remaining first metal layer to form the wiring layer.   
     
     
         5 . The method of  claim 1 , wherein the forming of a plurality of metal pillars in the step (C) further comprises the steps of:
 forming and patterning a second photo resist layer on the carrier;   forming a second metal layer on the patterned second photoresist layer; and   patterning the second metal layer by the removing of the second photoresist layer so as to form the plural metal pillars.   
     
     
         6 . The method of  claim 1 , wherein the first integrated-circuit chip further comprises:
 a plurality of first conductive pins, arranged connecting to the at least one metal wire while the first integrated-circuit chip is being disposed on the wiring layer.   
     
     
         7 . The method of  claim 1 , wherein the step (E) is performed using a means selected from the group consisting of: a top molding means, a compression molding means, a transfer molding means and an injection molding means. 
     
     
         8 . The method of  claim 7 , wherein the first molding compound layer is composed of a material selected from the group consisting of a novolac-based resin, an epoxy-based resin, and a silicon-based resin. 
     
     
         9 . The method of  claim 1 , wherein the step (F) uses polishing, grinding, sand blasting, plasma etching or chemical etching to remove the first molding compound layer in a top-down manner until the top ends of the plural metal pillars are exposed out of the covering of the first molding compound layer. 
     
     
         10 . The method of  claim 1 , wherein the second integrated-circuit chip further comprises:
 a plurality of second conductive pins, connecting to the exposed portions of the plural metal pillars while the second integrated-circuit chip is being disposed on the first molding compound layer.   
     
     
         11 . The method of  claim 1 , wherein the step (H) is performed using a means selected from the group consisting of: a top molding means, a compression molding means, a transfer molding means and an injection molding means. 
     
     
         12 . The method of  claim 11 , wherein the second molding compound layer is composed of a material selected from the group consisting of a novolac-based resin, an epoxy-based resin, and a silicon-based resin.