Nonvolatile semiconductor memory device

Abstract

A nonvolatile semiconductor memory device comprises a plurality of memory blocks, each including a plurality of cell units and each configured as a unit of execution of an erase operation. Each of the cell units comprises a memory string, a first transistor, a second transistor, and a diode. The first transistor has one end connected to one end of the memory string. The second transistor is provided between the other end of the memory string and a second line. The diode is provided between the other end of the first transistor and a first line. The diode comprises a second semiconductor layer of a first conductivity type and a third semiconductor layer of a second conductivity type.

1 . (canceled) 
     
     
         2 : A nonvolatile semiconductor memory device, comprising:
 a plurality of memory units including a plurality of memory cells and a first transistor, the plurality of memory units including a first memory unit and a second memory unit;   a first line coupled to a first terminal of the first memory unit and a first terminal of the second memory unit;   a second line coupled to a second terminal of the first memory unit;   a third line coupled to a second terminal of the second memory unit; and   a controller configured to perform a program operation, the controller being configured to apply a program voltage to a gate of a selected memory cell in the first memory unit in the program operation, the controller being configured to apply a first voltage to the second line and to apply a second voltage to the third line during a first period of the program operation, the first voltage being different from the second voltage, the controller being configured to be capable of applying a negative voltage to a gate of the first transistor in the first memory unit in the program operation.   
     
     
         3 : The nonvolatile semiconductor memory device according to  claim 2 , wherein the controller is configured to apply the negative voltage to the gate of the first transistor in the first memory unit during the first period. 
     
     
         4 : The nonvolatile semiconductor memory device according to  claim 2 , wherein one of the memory units includes a first columnar portion, a second columnar portion, and a connection portion, the first columnar portion and the second columnar portion extends in a stacking direction, and the connection portion extends in a first direction orthogonal to the stacking direction. 
     
     
         5 : The nonvolatile semiconductor memory device according to  claim 4 , wherein one of the memory units includes the plurality of memory cells stacked above a semiconductor substrate. 
     
     
         6 : The nonvolatile semiconductor memory device according to  claim 5 , wherein the first transistor is disposed above the memory cells. 
     
     
         7 : The nonvolatile semiconductor memory device according to  claim 2 , wherein the controller is configured to be capable of applying a positive voltage to a gate of the first transistor in the first memory unit when a program voltage is applied to the gate of the selected memory cell in the first memory unit. 
     
     
         8 : The nonvolatile semiconductor memory device according to  claim 6 , wherein the controller is configured to be capable of applying a positive voltage to a gate of the first transistor in the first memory unit when a program voltage is applied to the gate of the selected memory cell in the first memory unit. 
     
     
         9 : The nonvolatile semiconductor memory device according to  claim 2 , wherein the controller is configured to be capable of applying a pass voltage to gates of the memory cells in the first memory unit during the first period. 
     
     
         10 : The nonvolatile semiconductor memory device according to  claim 6 , wherein the controller is configured to be capable of applying a pass voltage to gates of the memory cells in the first memory unit during the first period. 
     
     
         11 : The nonvolatile semiconductor memory device according to  claim 8 , wherein the controller is configured to be capable of applying a pass voltage to gates of the memory cells in the first memory unit during the first period. 
     
     
         12 : The nonvolatile semiconductor memory device according to  claim 9 , wherein the controller is configured to perform an erase operation on a condition that an erase voltage is applied to the second line.