Offset voltage compensation

Abstract

A bridge offset voltage compensation method and circuit having a bridge circuit and a tunnel magnetoresistance (TMR) resistor cascade. The bridge circuit includes a branch circuit. The TMR resistor cascade is coupled in series with the branch circuit, and is configured to provide a resistance to compensate for a bridge offset voltage of the bridge circuit.

What is claimed is: 
     
         1 . A bridge offset voltage compensation circuit, comprising:
 a bridge circuit having a first branch circuit; and   a tunnel magnetoresistance (TMR) resistor cascade coupled in series with the first branch circuit, and configured to provide a resistance to compensate for a bridge offset voltage of the bridge circuit.   
     
     
         2 . The bridge offset voltage compensation circuit of  claim 1 , further comprising:
 a low ohmic metal line coupled in parallel to the TMR resistor cascade and having fuses,   wherein the fuses are configured to adjust the resistance of the TMR resistor cascade.   
     
     
         3 . The bridge offset voltage compensation circuit of  claim 2 , wherein the fuses are configured to break the low ohmic metal line at predetermined locations to establish a defined current flow path through the TMR resistor cascade. 
     
     
         4 . The bridge offset voltage compensation circuit of  claim 1 , further comprising:
 a low ohmic metal line coupled in parallel to the TMR resistor cascade and having switching elements,   wherein the switching elements are configured to adjust the resistance of the TMR resistor cascade.   
     
     
         5 . The bridge offset voltage compensation circuit of  claim 1 , wherein
 the TMR resistor cascade is coupled in series between the first branch circuit and a voltage source, and   the bridge offset voltage compensation circuit further comprises a further TMR resistor cascade coupled in series between the first branch circuit and a ground terminal.   
     
     
         6 . The bridge offset voltage compensation circuit of  claim 1 , wherein the resistance values of respective TMR resistors of the TMR resistor cascade increase by a factor of two. 
     
     
         7 . The bridge offset voltage compensation circuit of  claim 1 , wherein
 the bridge circuit has a second branch circuit coupled in parallel with the first branch circuit, and   bridge offset voltage compensation circuit further comprises a second TMR resistor cascade coupled in series to the second branch circuit, and configured to provide a resistance to compensate for the bridge offset voltage.   
     
     
         8 . The bridge offset voltage compensation circuit of  claim 7 , wherein the bridge circuit is a Wheatstone bridge. 
     
     
         9 . The bridge offset voltage compensation circuit of  claim 1 , further comprising:
 a plurality of contact pads coupled between respective TMR resistors of the TMR resistor cascade,   wherein the plurality of contact pads are configured to provide an applied voltage that is greater than a breakdown voltage to at least one of the TMR resistors of the TMR resistor cascade to short the at least one of the TMR resistors and lower the resistance of the TMR resistor cascade.   
     
     
         10 . The bridge offset voltage compensation circuit of  claim 1 , further comprising:
 a bottom electrode resistor cascade coupled in series with the TMR resistor cascade,   wherein the TMR resistor cascade has a negative temperature coefficient, and the bottom electrode resistor cascade has a positive temperature coefficient.   
     
     
         11 . The bridge offset voltage compensation circuit of  claim 10 , wherein a magnitude of the resistance of the TMR resistor cascade and a magnitude of the resistance of the bottom electrode resistor cascade are substantially equal. 
     
     
         12 . The bridge offset voltage compensation circuit of  claim 10 , wherein the bridge offset voltage has a temperature coefficient of zero or substantially close to zero. 
     
     
         13 . A sensor comprising the offset voltage compensation circuit of  claim 1 . 
     
     
         14 . A bridge offset voltage compensation circuit, comprising:
 a bridge circuit having a first branch circuit; and   a first cascade of resistors coupled in series with the first branch circuit and having a positive temperature coefficient; and   a second cascade of resistors coupled in series with the first branch circuit and the first cascade of resistors, and having a negative temperature coefficient,   wherein the first and second cascades of resistors are configured to provide a resistance to compensate for a bridge offset voltage of the bridge circuit, and the bridge offset voltage has a temperature coefficient of zero or substantially close to zero.   
     
     
         15 . A method of compensating for a bridge offset voltage, comprising:
 providing a bridge circuit having a branch circuit;   providing a tunnel magnetoresistance (TMR) resistor cascade coupled in series with the branch circuit;   measuring a bridge offset voltage of the bridge circuit; and   configuring, based on the measured bridge offset voltage, the resistance of the TMR resistor cascade to compensate for the bridge offset voltage of the bridge circuit.   
     
     
         16 . The method of  claim 15 ,
 further comprising providing a low ohmic metal line coupled in parallel with the TMR resistor cascade, and having fuses,   wherein the configuring step comprises breaking, using the fuses, the low ohmic metal line at predetermined locations to establish a defined current flow path through the TMR resistor cascade.   
     
     
         17 . The method of  claim 15 ,
 further comprising providing, for the TMR resistor cascade, a plurality of contact pads coupled between respective TMR resistors of the TMR resistor cascade,   wherein the configuring step comprises providing, using the plurality of contact pads, a voltage greater than a breakdown voltage to at least one of the TMR resistors to lower the resistance of the TMR resistor cascade.   
     
     
         18 . The method of  claim 15 ,
 further comprising providing a bottom electrode resistor cascade coupled in series with the TMR resistor cascade,   wherein the TMR resistor cascade has a negative temperature coefficient, and the bottom electrode resistor cascade has a positive temperature coefficient.   
     
     
         19 . The method of  claim 18 ,
 further comprising providing a low ohmic metal line coupled in parallel with the TMR resistor cascade and the bottom electrode resistor cascade, wherein the low ohmic metal line has fuses,   wherein the configuring step comprises breaking, using the fuses, the low ohmic metal line at predetermined locations to establish a defined current flow path through the TMR resistor cascade and the bottom electrode resister cascade.   
     
     
         20 . The method of  claim 15 , wherein the configuring step comprises:
 calculating a variable α in accordance with the equation   
       
         
           
             
               
                 α 
                 = 
                 
                   
                     Tk_Offset 
                     target 
                   
                   
                     
                        
                       
                         Tk_R 
                         TMR 
                       
                        
                     
                     + 
                     
                        
                       
                         Tk_R 
                         Bottom 
                       
                        
                     
                   
                 
               
               , 
             
           
         
          where Tk_Offset target  is a measured temperature coefficient of the bridge offset voltage of the bridge circuit, and 
         if a sign of the variable α is negative, a compensation resistance of the TMR resistor cascade is R TMR =(1−α)·R Corr , and a compensation resistance of the bottom electrode resistor cascade is R bottom =α·R Corr , and 
         if the sign of the variable α is positive, the compensation resistance of the TMR resistor cascade is R TMR =α·R Corr , and the compensation resistance of the bottom electrode resistor cascade is R bottom =(1−α)·R Corr , 
       
       where R Corr  is a resistance needed to compensate for the bridge offset voltage of the bridge circuit.