Semiconductor structure with nanowire structures and manufacturing method thereof

Abstract

The present invention provides a semiconductor structure, including a substrate, a first nanowire structure disposed on the substrate, and the first nanowire structure includes a gate region and a source/drain region The diameter of the first nanowire structure within the gate region is different from the diameter of the first nanowire structure within the source/drain region.

What is claimed is: 
     
         1 . A semiconductor structure, comprising:
 a substrate; and   a first nanowire structure disposed on the substrate, the first nanowire structure including a gate region and at least one source/drain (S/D) region, wherein the diameter within the gate region of the first nanowire structure is different from the diameter within the S/D region of the first nanowire structure.   
     
     
         2 . The semiconductor structure of  claim 1 , wherein the diameter within the gate region of the first nanowire structure is larger than the diameter within the S/D region of the first nanowire structure. 
     
     
         3 . The semiconductor structure of  claim 1 , wherein the diameter within the gate region of the first nanowire structure is smaller than the diameter within the S/D region of the first nanowire structure. 
     
     
         4 . The semiconductor structure of  claim 1 , further comprising a second nanowire structure disposed on the substrate, wherein the second nanowire structure includes a gate region and at least one S/D region. 
     
     
         5 . The semiconductor structure of  claim 4 , wherein the diameter within the gate region of the second nanowire structure is different from the diameter within the gate region of the first nanowire structure. 
     
     
         6 . The semiconductor structure of  claim 4 , wherein the diameter within the S/D region of the second nanowire structure is different from the diameter within the S/D region of the first nanowire structure. 
     
     
         7 . A method for forming a semiconductor structure, comprising:
 providing a substrate, the substrate comprising an insulating layer and at least one first nano channel structure disposed thereon, a first region and a second region being defined on the substrate;   forming a hard mask within the first region, to cover the first nano channel structure and the insulating layer;   performing an etching process, to remove parts of the insulating layer within the second region;   performing an epitaxial process, to form an epitaxial layer on the first nano channel structure, wherein the thickness of the epitaxial layer within the first region is different from the thickness of the epitaxial layer within the second region; and   performing an anneal process, to transform the first nano channel structure and the epitaxial layer into a first nanowire structure, wherein the diameter of the first nanowire structure within the first region is different from the diameter of the first nanowire structure within the second region.   
     
     
         8 . The method of  claim 7 , wherein a gate region of the first nanowire structure is disposed within the first region, and a source/drain (S/D) region of the first nanowire structure is disposed within the second region. 
     
     
         9 . The method of  claim 7 , wherein a source/drain (S/D) region of the first nanowire structure is disposed within the first region, and a gate region of the first nanowire structure is disposed within the second region. 
     
     
         10 . The method of  claim 7 , wherein the epitaxial layer comprises a silicon germanium layer. 
     
     
         11 . The method of  claim 7 , further comprising forming a second nanowire structure on the substrate, wherein the second nanowire structure comprises a gate region and at least one S/D region. 
     
     
         12 . The method of  claim 11 , wherein the diameter of the second nanowire structure within its gate region is different from the diameter of the first nanowire structure within its gate region. 
     
     
         13 . The method of  claim 11 , wherein the diameter of the second nanowire structure within its S/D region is different from the diameter of the first nanowire structure within its S/D region. 
     
     
         14 . The method of  claim 11 , wherein the method for forming the second nanowire structure comprising:
 forming a second nano channel structure on the substrate;   forming an oxide layer to cover the first nano channel structure, but not covering the second nano channel structure; and   performing an anneal process, to transform the second nano channel structure into the second nanowire structure.   
     
     
         15 . The method of  claim 7 , wherein the etching process is performed before the epitaxial process is performed. 
     
     
         16 . The method of  claim 7 , wherein the etching process is performed after the epitaxial process is performed.