Metal-insulator-metal capacitor structure

Abstract

A capacitor structure in a semiconductor device includes a semiconductor substrate having a top surface and a bottom surface opposite the top surface, an isolation region having a top surface and a bottom surface, opposite the top surface, the bottom surface of the isolation region being disposed on the top surface of the semiconductor substrate. The capacitor structure also includes a gate terminal structure disposed on the top surface of the isolation region and a diffusion contact structure disposed on the top surface of the isolation region and arranged parallel to the gate terminal structure. In some aspects, the gate terminal structure is connected to a first contact node and the diffusion contact structure is connected to a second contact node, in which the first and second contact nodes form opposing nodes of the capacitor structure.

What is claimed is: 
     
         1 . A capacitor structure, comprising:
 a semiconductor substrate;   a first isolation layer disposed on a top surface of the semiconductor substrate;   a first gate terminal structure disposed on a top surface of the first isolation layer;   a second gate terminal structure disposed on the top surface of the first isolation layer;   a first etch-stop structure disposed on a top surface of the first gate terminal structure;   a second isolation layer disposed on a top surface of the first etch-stop structure; and   a contact structure disposed on the first isolation layer and in contact with a sidewall of the first gate terminal structure and a sidewall of the second gate terminal structure, the contact structure being a block of first conductive material that extends across at least a portion of the first gate terminal structure and the second gate terminal structure, the contact structure extending through at least a portion of the second isolation layer and contacting the first etch-stop structure, the first gate terminal structure coupled to a first contact node and the contact structure coupled to a second contact node, the first contact node and the second contact node forming opposite nodes of the capacitor structure.   
     
     
         2 . The capacitor structure of  claim 1 , wherein a first portion of the contact structure is disposed within a first etched cavity and a second portion of the contact structure is disposed within a second etched cavity, the first gate terminal structure being located between the first etched cavity and the second etched cavity. 
     
     
         3 . The capacitor structure of  claim 2 , wherein the first gate terminal structure comprises:
 a first wall spacer;   a second wall spacer opposite of the first wall spacer; and   a gate filler disposed between the first wall spacer and the second wall spacer, the gate filler comprising a second conductive material,   wherein a first sidewall of the contact structure contacts the first wall spacer of the first gate terminal structure within the first etched cavity and a second sidewall of the contact structure contacts the second wall spacer of the first gate terminal structure within the second etched cavity, and   wherein the first wall spacer and the second wall spacer isolate the second conductive material of the gate filler from the first conductive material of the contact structure.   
     
     
         4 . The capacitor structure of  claim 3 , wherein the first etch-stop structure is coupled to a top surface of the gate filler, and wherein the first etch-stop structure isolates the first conductive material from the second conductive material. 
     
     
         5 . The capacitor structure of  claim 2 , further comprising:
 a third gate terminal structure disposed on the top surface of the first isolation layer,   wherein the first gate terminal structure is located between the second gate terminal structure and the third gate terminal structure, and   wherein a third sidewall of the contact structure contacts a wall spacer of the second gate terminal structure within the second etched cavity and a fourth sidewall of the contact structure contacts a wall spacer of the third gate terminal structure within the first etched cavity.   
     
     
         6 . The capacitor structure of  claim 5 , further comprising:
 a second etch-stop structure disposed on a top surface of the second gate terminal structure; and   a third etch-stop structure disposed on a top surface of the third gate terminal structure,   wherein the contact structure extends through the second isolation layer and contacts the second etch-stop structure and the third etch-stop structure.   
     
     
         7 . The capacitor structure of  claim 6 , further comprising a third isolation layer disposed on the top surface of the first isolation layer, wherein the second isolation layer is disposed on a top surface of the third isolation layer, and wherein the top surface of the third isolation layer is coplanar with a top surface of the second etch-stop structure and a top surface of the third etch-stop structure. 
     
     
         8 . The capacitor structure of  claim 1 , wherein the semiconductor substrate comprises a plurality of fin-shaped structures formed at the top surface of the semiconductor substrate and in contact with the contact structure, the first gate terminal structure and the second gate terminal structure, and wherein the contact structure extends across the plurality of fin-shaped structures. 
     
     
         9 . The capacitor structure of  claim 1 , further comprising first contacts formed on one end of the first gate terminal structure and the second gate terminal structure and second contacts formed on opposite corners of the contact structure, wherein the first contacts are coupled to a same metallization layer and the second contacts are coupled to respective metallization layers. 
     
     
         10 . The capacitor structure of  claim 1 , further comprising first contacts formed on centered locations of the first gate terminal structure and the second gate terminal structure and second contacts formed on centered locations of the contact structure, wherein the first contacts are coupled to a first metallization layer and the second contacts are coupled to a second metallization layer. 
     
     
         11 . A semiconductor device, comprising:
 a semiconductor substrate;   an isolation structure disposed on a top surface of the semiconductor substrate;   a first gate terminal structure in contact with the isolation structure;   a second gate terminal structure in contact with the isolation structure;   a third gate terminal structure in contact with the isolation structure, the first gate terminal structure;   a first etch-stop structure disposed on a top surface of the second gate terminal structure; and   a contact structure in contact with the isolation structure, the contact structure extending through at least a portion of the isolation structure and contacting the first etch-stop structure, a sidewall of the first gate terminal structure and a sidewall of the third gate terminal structure, the contact structure being a block of first conductive material that extends between the first gate terminal structure and the third gate terminal structure, the first gate terminal structure coupled to a first contact node and the contact structure coupled to a second contact node, the first contact node and the second contact node forming opposite nodes of the semiconductor device.   
     
     
         12 . The semiconductor device of  claim 11 , wherein a first portion of the contact structure is disposed within a first etched cavity and a second portion of the contact structure is disposed within a second etched cavity, the first gate terminal structure being located between the first etched cavity and the second etched cavity, the contact structure comprising a first conductive material. 
     
     
         13 . The semiconductor device of  claim 12 , wherein the first gate terminal structure comprises:
 a first wall spacer;   a second wall spacer opposite of the first wall spacer; and   a gate filler disposed between the first wall spacer and the second wall spacer, the gate filler comprising a second conductive material,   wherein a first sidewall of the contact structure contacts the first wall spacer of the first gate terminal structure within the first etched cavity and a second sidewall of the contact structure contacts the second wall spacer of the first gate terminal structure within the second etched cavity, and   wherein the first wall spacer and the second wall spacer isolate the second conductive material of the gate filler from the first conductive material of the conductive structure.   
     
     
         14 . The semiconductor device of  claim 13 , wherein the first etch-stop structure is coupled to a top surface of the gate filler, and wherein the first etch-stop structure isolates the first conductive material from the second conductive material. 
     
     
         15 . The semiconductor device of  claim 11 , further comprising:
 a second etch-stop structure disposed on a top surface of the first gate terminal structure; and   a third etch-stop structure disposed on a top surface of the third gate terminal structure,   wherein the contact structure extends through the isolation structure and contacts the second etch-stop structure and the third etch-stop structure.   
     
     
         16 . The semiconductor device of  claim 11 , wherein the semiconductor substrate comprises a plurality of fin-shaped structures formed at the top surface of the semiconductor substrate and in contact with the contact structure, the first gate terminal structure and the second gate terminal structure, and wherein the contact structure extends across the plurality of fin-shaped structures. 
     
     
         17 . The semiconductor device of  claim 11 , further comprising first contacts formed on one end of the first gate terminal structure and the second gate terminal structure and second contacts formed on opposite corners of the contact structure, wherein the first contacts are coupled to a same metallization layer and the second contacts are coupled to respective metallization layers. 
     
     
         18 . The semiconductor device of  claim 11 , further comprising first contacts formed on centered locations of the first gate terminal structure and the second gate terminal structure and second contacts formed on centered locations of the contact structure, wherein the first contacts are coupled to a first metallization layer and the second contacts are coupled to a second metallization layer. 
     
     
         19 . The semiconductor device of  claim 11 , wherein the isolation structure comprises a plurality of isolation layers, wherein a first isolation layer of the plurality of isolation layers is disposed on the top surface of the semiconductor substrate, wherein a second isolation layer of the plurality of isolation layers is disposed on a top surface of the first isolation layer, wherein a third isolation layer of the plurality of isolation layers is disposed on a top surface of the second isolation layer. 
     
     
         20 . A capacitor structure in a semiconductor device, the capacitor structure comprising:
 a semiconductor substrate;   an isolation structure disposed on a top surface of the semiconductor substrate;   a gate terminal structure in contact with the isolation structure;   an etch-stop structure disposed on a top surface of the gate terminal structure; and   a contact structure extending through at least a portion of the isolation structure and contacting the etch-stop structure, the contact structure having a first portion disposed within a first etched cavity and a second portion disposed within a second etched cavity, the gate terminal structure disposed between the first etched cavity and the second etched cavity, the contact structure being a block of first conductive material that extends more than half of a length of the gate terminal structure in a first direction and beyond a width of the gate terminal structure in a second direction orthogonal to the first direction, the first portion of the contact structure contacting a first sidewall of the gate terminal structure and the second portion of the contact structure contacting a second sidewall of the gate terminal structure, the gate terminal structure coupled to a first contact node and the contact structure coupled to a second contact node, the first contact node and the second contact node forming opposite nodes of the capacitor structure.