Wafer level semiconductor package and manufacturing methods thereof

Abstract

A semiconductor package includes at least one semiconductor die having an active surface, an interposer element having an upper surface and a lower surface, a package body, and a lower redistribution layer. The interposer element has at least one conductive via extending between the upper surface and the lower surface. The package body encapsulates portions of the semiconductor die and portions of the interposer element. The lower redistribution layer electrically connects the interposer element to the active surface of the semiconductor die.

1 - 20 . (canceled) 
     
     
         21 . A method of forming a semiconductor package, the method comprising:
 providing a semiconductor die;   placing a connecting element adjacent to the die, the connecting element having a first surface and a second surface opposite to the first surface;   encapsulating portions of the semiconductor die and portions of the connecting element with an encapsulant, the encapsulant having a first surface and a second surface opposite to the first surface, wherein the second surface of the connecting element and the second surface of the encapsulant form a substantially coplanar surface; and   forming a first redistribution layer on the substantially coplanar surface, the first redistribution layer electrically connecting the connecting element to the semiconductor die.   
     
     
         22 . The method of  claim 21 , further comprising removing a portion of the encapsulant to expose the second surface of the connecting element, prior to forming the first redistribution layer. 
     
     
         23 . The method of  claim 21 , wherein encapsulating portions of the semiconductor die and portions of the connecting element comprises surrounding a lateral periphery of the connecting element with the encapsulant. 
     
     
         24 . The method of  claim 21 , further comprising:
 forming a second redistribution layer on the first surface of the connecting element and the first surface of the encapsulant.   
     
     
         25 . The method of  claim 24 , further comprising electrically connecting the first redistribution layer to the second redistribution layer through the connecting element. 
     
     
         26 . The method of  claim 21 , further comprising electrically connecting a device external to the semiconductor package via the first redistribution layer. 
     
     
         27 . The method of  claim 24 , further comprising electrically connecting an electrical component to the second redistribution layer. 
     
     
         28 . The method of  claim 21 , further comprising placing the semiconductor die and the connecting element on a carrier. 
     
     
         29 . The method of  claim 28 , further comprising removing the carrier after encapsulating portions of the semiconductor die and portions of the connecting element. 
     
     
         30 . The method of  claim 21 , wherein the connecting element comprises metal. 
     
     
         31 . A semiconductor package structure comprising:
 a semiconductor die, the semiconductor die having a first surface, a second surface opposite to the first surface, and a side surface extending from the first surface to the second surface;   a connecting element adjacent to the die, the connecting element having a first surface and a second surface opposite to the first surface;   an encapsulant covering portions of the semiconductor die and portions of the connecting element, the encapsulant having a first surface and a second surface opposite to the first surface, the second surface of the connecting element and the second surface of the encapsulant forming a substantially coplanar surface; and   a first redistribution layer on the substantially coplanar surface, the first redistribution layer electrically connecting the connecting element to the semiconductor die.   
     
     
         32 . The semiconductor package structure of  claim 31 , further comprising a second redistribution layer on the first surface of the connecting element and the first surface of the encapsulant. 
     
     
         33 . The semiconductor package structure of  claim 32 , wherein the first redistribution layer and the second redistribution layer are electrically connected through the connecting element. 
     
     
         34 . The semiconductor package structure of  claim 31 , further comprising a device external to the semiconductor package electrically connected to the first redistribution layer. 
     
     
         35 . The semiconductor package structure of  claim 31 , further comprising a bump electrically connected to the connecting element. 
     
     
         36 . The semiconductor package structure of  claim 31 , wherein the encapsulant covers at least a portion of the first surface of the semiconductor die and at least a portion of the side surface of the semiconductor die. 
     
     
         37 . The semiconductor package structure of  claim 31 , wherein the connecting element comprises metal.