Fan out of result of explicit data graph execution instruction

Abstract

An apparatus for fan out of a result of a first instruction can include first through fourth sets of memory cells and circuitry. The first set can be configured to store the result of the first instruction. The second set can be configured to store an operation code of a second instruction. The third set can be configured to store information of the second instruction. The fourth set can be configured to store an operand for the second instruction. The circuitry can be configured to connect the fourth set to an execution unit and to cause, in response to a presence of the information in the third set, the execution unit to be configured to receive a content of the first set as the operand for the second instruction. A format of the second instruction can include a sets of bits designated for the operation code and for the information.

What is claimed is: 
     
         1 . An apparatus for fan out of a result of a first instruction, the apparatus comprising:
 memory cells including:
 a first set configured to store the result of the first instruction; 
 a second set configured to store an operation code of a second instruction; 
 a third set configured to store an information of the second instruction; and 
 a fourth set configured to store an operand for the second instruction; and 
   a first circuitry configured to connect the fourth set to an execution unit and configured to cause, in response to a presence of the information in the third set, the execution unit to be configured to receive a content of the first set as the operand for the second instruction;   wherein the first set, the second set, the third set, and the fourth set are disjoint; and   wherein a format of the second instruction includes a set of bits designated for the operation code and a set of bits designated for the information.   
     
     
         2 . The apparatus of  claim 1 , wherein:
 each memory cell of the second set comprises a random access memory cell; and   each memory cell of the third set comprises a flip-flop.   
     
     
         3 . The apparatus of  claim 1 , wherein the first circuitry comprises at least one switch. 
     
     
         4 . The apparatus of  claim 3 , wherein the at least one switch comprises at least one of a relay, a microelectromechanical switch, a semiconductor device, a transistor, a multiplexer, a pass gate, or any combination thereof. 
     
     
         5 . The apparatus of  claim 1 , wherein:
 a record of a reservation station of an array of reservation stations includes the second set, the third set, and the fourth set; and   the array of reservation stations excludes the first set.   
     
     
         6 . The apparatus of  claim 1 , wherein the first set includes a first subset and a second subset, the fourth set includes a third subset and a fourth subset, the third subset configured to store a first operand for the second instruction, the fourth subset configured to store a second operand for the second instruction, and the first circuitry is configured to cause, in response to the presence of the information in the third set, the execution unit to be configured to receive a content of the first subset as the first operand for the second instruction and a content of the second subset as the second operand for the second instruction. 
     
     
         7 . The apparatus of  claim 1 , wherein the first set includes a first subset and a second subset, the third set includes a third subset and a fourth subset, the fourth set includes a fifth subset and a sixth subset, the third subset configured to store a first information of the second instruction, the fourth subset configured to store a second information of the second instruction, the fifth subset configured to store a first operand for the second instruction, the sixth subset configured to store a second operand for the second instruction, and the first circuitry is configured to cause:
 in response to a presence of the first information in the third subset, the execution unit to be configured to receive a content of the first subset as the first operand for the second instruction; and   in response to a presence of the second information in the fourth subset, the execution unit to be configured to receive a content of the second subset as the second operand for the second instruction.   
     
     
         8 . The apparatus of  claim 1 , wherein the memory cells further comprise a fifth set configured to store a predicate operand of the second instruction, the format of the second instruction further includes a set of bits designated for the predicate operand, the first set includes a first subset and a second subset, and the first circuitry is configured to cause, in response to the presence of the information in the third set:
 the execution unit to be configured to receive a content of the first subset as the operand for the second instruction; and   the fifth set to be configured to receive a content of the second subset as the predicate operand of the second instruction.   
     
     
         9 . The apparatus of  claim 1 , wherein the memory cells further comprise a fifth set configured to store a predicate operand of the second instruction, the format of the second instruction further includes a set of bits designated for the predicate operand, the first set includes a first subset and a second subset, the third set includes a third subset and a fourth subset, the third subset configured to store a first information of the second instruction, the fourth subset configured to store a second information of the second instruction, and the first circuitry is configured to cause:
 in response to a presence of the first information in the third subset, the execution unit to be configured to receive a content of the first subset as the operand for the second instruction; and   in response to a presence of the second information in the fourth subset, the fifth set to be configured to receive a content of the second subset as the predicate operand of the second instruction.   
     
     
         10 . The apparatus of  claim 1 , wherein the memory cells further comprise a fifth set configured to store the result of the first instruction, the information is configured to have one of a first value or a second value, and the first circuitry is configured to cause:
 in response to the presence of the information having the first value in the third set, the execution unit to be configured to receive the content of the first set as the operand for the second instruction; and   in response to the presence of the information having the second value in the third set, the execution unit to be configured to receive a content of the fifth set as the operand for the second instruction.   
     
     
         11 . The apparatus of  claim 1 , further comprising a second circuitry configured to prevent the execution unit from being configured to receive the content of the first set until after the result of the first instruction has been stored in the first set. 
     
     
         12 . The apparatus of  claim 11 , wherein the memory cells further comprise a fifth set configured to store the result of the first instruction, and the second circuitry is further configured to prevent the execution unit from being configured to receive a content of the fifth set until after the result of the first instruction has been stored in the fifth set. 
     
     
         13 . The apparatus of  claim 1 , wherein the first set includes a first subset and a second subset, and further comprising a second circuitry configured to prevent the execution unit from being configured to receive the content of the first set until after the result of the first instruction has been stored in at least one of the first subset or the second subset. 
     
     
         14 . The apparatus of  claim 1 , wherein the first set includes a first subset and a second subset, and further comprising a second circuitry configured to prevent the execution unit from being configured to receive:
 a content of the first subset until after the result of the first instruction has been stored in the first subset; and   a content of the second subset until after the result of the first instruction has been stored in the second subset.   
     
     
         15 . The apparatus of  claim 1 , wherein the first set includes a first subset and a second subset, the memory cells further comprise a fifth set configured to store a predicate operand of the second instruction, the format of the second instruction further includes a set of bits designated for the predicate operand, and further comprising a second circuitry configured to prevent the execution unit and the fifth set from being configured to receive the content of the first set until after the result of the first instruction has been stored in at least one of the first subset or the second subset. 
     
     
         16 . The apparatus of  claim 1 , wherein the first set includes a first subset and a second subset, the memory cells further comprise a fifth set configured to store a predicate operand of the second instruction, the format of the second instruction further includes a set of bits designated for the predicate operand, and further comprising a second circuitry configured to prevent:
 the execution unit from being configured to receive a content of the first subset until after the result of the first instruction has been stored in the first subset; and   the fifth set from being configured to receive a content of the second subset until after the result of the first instruction has been stored in the second subset.   
     
     
         17 . An apparatus for fan out of a result of a first instruction, the apparatus comprising:
 means for storing the result of the first instruction;   means for storing an operation code of a second instruction;   means for storing an information of the second instruction;   means for storing an operand for the second instruction; and   means for causing, in response to a presence of the information in the means for storing the information, means for executing the second instruction to be configured to receive a content of the means for storing the result as the operand for the second instruction;   wherein the means for storing the results, the means for storing the operation code, the means for storing the information, and the means for storing the operand are disjoint; and   wherein a format of the second instruction includes a set of bits designated for the operation code and a set of bits designated for the information.   
     
     
         18 . The apparatus of  claim 17 , further comprising means for preventing the means for executing the second instruction from being configured to receive the content of the means for storing the result until after the result of the first instruction has been stored in the means for storing the result. 
     
     
         19 . A method for fan out of a result of a first instruction, the method comprising:
 storing the result of the first instruction in a first set of memory cells;   storing an operation code of a second instruction in a second set of memory cells;   storing an information of the second instruction in a third set of memory cells;   providing a fourth set of memory cells configured to store an operand for the second instruction; and   causing, in response to a presence of the information in the third set of memory cells, an execution unit to be configured to receive a content of the first set of memory cells as the operand for the second instruction;   wherein the first set of memory cells, the second set of memory cells, the third set of memory cells, and the fourth set of memory cells are disjoint; and   wherein a format of the second instruction includes a set of bits designated for the operation code and a set of bits designated for the information.   
     
     
         20 . A computer processor core, comprising:
 an array having a reservation station, the reservation station having a first record, the first record having a first set of memory cells and a second set of memory cells, the first set of memory cells configured to store an operation code of a first instruction, the second set of memory cells configured to store a first information of the first instruction, the second set of memory cells and the first set of memory cells being disjoint, a format of the first instruction including a set of bits designated for the operation code and a set of bits designated for the first information, the first instruction being of a block of instructions, the block of instructions configured according to a block-based instruction set architecture; and   a circuitry configured to make a determination of a presence of the first information in the second set of memory cells, to select, in response to the determination, a source of an operand for the first instruction, and to execute the block of instructions as a unit.   
     
     
         21 . The computer processor core of  claim 20 , wherein the first record further includes a third set of memory cells configured to store an identity of a destination of a result of the first instruction, and wherein the format of the first instruction further includes a set of bits designated for the identity of the destination of the result of the first instruction. 
     
     
         22 . The computer processor core of  claim 21 , wherein the array has a second record, the second record having a fourth set of memory cells, the fourth set of memory cells configured to store an operand for a second instruction, and wherein the circuitry is further configured so that the fourth set of memory cells is a first candidate for the destination of the result of the first instruction. 
     
     
         23 . The computer processor core of  claim 22 , further comprising a fifth set of memory cells configured to store the result of the first instruction, wherein the array excludes the fifth set of memory cells, wherein the fifth set of memory cells is different from a register of a physical register file of the computer processor core, wherein the circuitry is further configured so that the fifth set of memory cells is a second candidate for the destination of the result of the first instruction, and wherein the circuitry is further configured so that data stored in the fifth set of memory cells are accessible by any execution unit that corresponds to the array without a requirement that the data traverse a cache between the fifth set of memory cells and the any execution unit. 
     
     
         24 . The computer processor core of  claim 20 , wherein the first record further includes a third set of memory cells configured to store an operand for the first instruction and further comprising a fourth set of memory cells, wherein the array excludes the fourth set of memory cells, wherein the fourth set of memory cells is different from a register of a physical register file of the computer processor core, wherein the circuitry is further configured so that data stored in the fourth set of memory cells are accessible by any execution unit that corresponds to the array without a requirement that the data traverse a cache between the fourth set of memory cells and the any execution unit, and wherein the circuitry is configured to select, in response to the presence of the first information in the second set of memory cells, a content of the fourth set of memory cells as the source of the operand for the first instruction. 
     
     
         25 . The computer processor core of  claim 24 , further comprising a fifth set of memory cells, wherein the array excludes the fifth set of memory cells, wherein the fifth set of memory cells is different from the register, wherein the circuitry is further configured so that data stored in the fifth set of memory cells are accessible by the any execution unit without the requirement that the data traverse the cache between the fifth set of memory cells and the any execution unit, wherein the first information includes at least one of a first information or a second first information, and wherein the circuitry is configured to select:
 in response to a presence of the first information in the second set of memory cells, the content of the fourth set of memory cells as the source of the operand for the first instruction; and   in response to a presence of the second first information in the second set of memory cells, the content of the fifth set of memory cells as the source of the operand for the first instruction.   
     
     
         26 . The computer processor core of  claim 20 , wherein the first record further includes a third set of memory cells configured to store a predicate operand of the first instruction, and wherein the format of the first instruction further includes a set of bits designated for the predicate operand. 
     
     
         27 . The computer processor core of  claim 26 , further comprising a fourth set of memory cells, wherein the array excludes the fourth set of memory cells, wherein the fourth set of memory cells is different from a register of a physical register file of the computer processor core, wherein the circuitry is further configured so that data stored in the fourth set of memory cells are accessible by any execution unit that corresponds to the array without a requirement that the data traverse a cache between the fourth set of memory cells and the any execution unit, and wherein the circuitry is configured to select, in response to the presence of the information in the second set of memory cells, a content of the fourth set of memory cells as the source of the predicate operand of the first instruction. 
     
     
         28 . The computer processor core of  claim 20 , wherein the first record further includes:
 a third set of memory cells configured to store a second information, wherein the format of the first instruction further includes a set of bits designated for the second information, a presence of the second information in the third set of memory cells indicative that the first instruction needs a predicate operand;   a fourth set of memory cells configured to store a third information, wherein the format of the first instruction further includes a set of bits designated for the third information, a presence of the third information in the fourth set of memory cells indicative that the predicate operand needs to have a true value;   a fifth set of memory cells configured to store a fourth information, wherein a presence of the fourth information in the fifth set of memory cells is indicative that the predicate operand has been received by the first instruction; and   a sixth set of memory cells configured to store a fifth information, wherein a presence of the fifth information in the sixth set of memory cells is indicative that the predicate operand, received by the first instruction, has the true value.   
     
     
         29 . The computer processor core of  claim 20 , wherein the first record further includes:
 a third set of memory cells configured to store a second information, wherein the format of the first instruction further includes a set of bits designated for the second information, a presence of the second information in the third set of memory cells indicative that the first instruction needs a predicate operand;   a fourth set of memory cells configured to store a third information, wherein the format of the first instruction further includes a set of bits designated for the third information, a presence of the third information in the fourth set of memory cells indicative that the predicate operand needs to have a true value;   a fifth set of memory cells configured to store a fourth information, wherein a presence of the fourth information in the fifth set of memory cells is indicative that the predicate operand has been received by the first instruction and the predicate operand has the true value; and   a sixth set of memory cells configured to store a fifth information, wherein a presence of the fifth information in the sixth set of memory cells is indicative that the predicate operand has been received by the first instruction and the predicate operand has a false value.   
     
     
         30 . The computer processor core of  claim 20 , wherein the first record further includes:
 a third set of memory cells configured to store a first operand for the first instruction;   a fourth set of memory cells configured to store a second information, wherein the format of the first instruction further includes a set of bits designated for the second information, a presence of the second information in the fourth set of memory cells indicative that the first instruction needs the first operand;   a fifth set of memory cells configured to store a third information, wherein a presence of the third information in the fifth set of memory cells is indicative that an execution unit that corresponds to the first record has received the first operand;   a sixth set of memory cells configured to store a second operand for the first instruction;   a seventh set of memory cells configured to store a fourth information, wherein the format of the first instruction further includes a set of bits designated for the fourth information, a presence of the fourth information in the seventh set of memory cells indicative that the first instruction needs the second operand; and   an eighth set of memory cells configured to store a fifth information, wherein a presence of the fifth information in the eighth set of memory cells is indicative that the execution unit has received the second operand.