Solid state memory (ssm), computer system including an ssm, and method of operating an ssm

Abstract

In one aspect, data is stored in a solid state memory which includes first and second memory layers. A first assessment is executed to determine whether received data is hot data or cold data. Received data which is assessed as hot data during the first assessment is stored in the first memory layer, and received data which is first assessed as cold data during the first assessment is stored in the second memory layer. Further, a second assessment is executed to determine whether the data stored in the first memory layer is hot data or cold data. Data which is then assessed as cold data during the second assessment is migrated from the first memory layer to the second memory layer.

1 . A memory system, comprising:
 a first group of flash memory cells, each of the first group of flash memory cells configured to store one bit per cell;   a second group of flash memory cells, each of the second group of flash memory cells configured to store two or more bits per cell; and   a controller in communication with the first group of flash memory cells and the second group of flash memory cells, wherein the controller is configured to receive input data from a host and write the input data to one of the first group of flash memory cells and the second group of flash memory cells based on the size of the input data, and the controller is further configured to migrate first data from the first group of flash memory cells to the second group of flash memory cells if the number of available memory cells in the first group of flash memory cell is less than a first threshold,   wherein the controller is configured to write the input data to the first group of flash memory cells if the size of the input data is less than the second threshold, and   wherein the controller is configured to write the input data to the second group of flash memory cells, bypassing the first group of flash memory cells, if the size of the input data is equal to or greater than the second threshold.   
     
     
         2 . The memory system of  claim 1 , wherein the first threshold is greater than zero. 
     
     
         3 . The memory system of  claim 2 , wherein the first group of flash memory cells and the second group of flash memory cells are within a memory device. 
     
     
         4 . The memory system of  claim 1 , wherein the migrating the first data occurs at given periodic intervals. 
     
     
         5 . The memory system of  claim 1 , wherein the migrating the first data occurs when the memory system is an idle state, wherein the idle state includes periods in which no read or write request is received. 
     
     
         6 . The memory system of  claim 2 , wherein the controller is further configured to select the first data among data stored in the first group of memory cells based on a write access frequency of the first data, and migrate the first data from the first group of memory cells to the second group of memory cells. 
     
     
         7 . The memory system of  claim 6 , wherein the controller is further configured to manage a logical block address access for the selection of the first data. 
     
     
         8 . A method of storing data to a memory system including a first group of flash memory cells, each of the first group of flash memory cells storing one bit per cell, a second group of memory flash memory cells, each of the second group of flash memory cells storing two or more bit per cell, a controller in communication with the first group of flash memory cells and the second group of flash memory cells, and a volatile memory device, the method comprising:
 receiving input data from a host and storing the input data in the volatile memory device via the controller;   writing the input data to one of the first group of flash memory cells and the second group of flash memory cells via the controller based on the size of the input data; and   migrating first data from the first group of flash memory cells to the second group of flash memory cells if the number of available memory cells in the first group of flash memory cells is less than a first threshold.   wherein the writing the input data is performed to the first group of flash memory cells if the size of the input data is less than a second threshold, and   wherein the controller is configured to write the input data to the second group of flash memory cells, bypassing the first group of flash memory cells, if the size of the input data is equal to or greater than the second threshold.   
     
     
         9 . The method of  claim 8 , wherein the first threshold is greater than zero. 
     
     
         10 . The method of  claim 8 , wherein the migrating occurs at given periodic intervals. 
     
     
         11 . The method of  claim 8 , wherein the migrating occurs when the memory system is an idle state. 
     
     
         12 . The method of  claim 11 , the idle state is an activation intensity of read or write request is less than a threshold. 
     
     
         13 . The method of  claim 11 , the idle state includes periods in which no read or write request is received. 
     
     
         14 . A storage device using semiconductor memory comprising:
 a first group of flash memory cells, each of the first group of flash memory cells configured to store one bit per cell;   a second group of flash memory cells, each of the second group of flash memory cells configured to store two or more bits per cell;   a controller configured to receive input data from a host via a first interface, and to write the input data, via a second interface, to one of the first group of flash memory cells and the second group of flash memory cells based on the size of the input data, and the controller is further configured to migrate first data from the first group of flash memory cells to the second group of flash memory cells if the number of available memory cells in the first group of flash memory cells is less than a first threshold; and   a volatile memory device in communication with the controller via a third interface to store at least a portion of the input data temporarily before the input data is written to one of the first group of flash memory cells and the second group of flash memory cells.   
     
     
         15 . The storage device using semiconductor memory of  claim 14 , wherein the controller is configured to write the input to the first group of flash memory cells if the size of the input data is less than the second threshold. 
     
     
         16 . The storage device using semiconductor memory of  claim 15 , wherein the controller is configured to write the input data to the second group of flash memory cells, bypassing the first group of flash memory cells, if the size of the input data is equal to or greater than the second threshold. 
     
     
         17 . The storage device using semiconductor memory of  claim 16 , wherein the first group of flash memory cells and the second group of flash memory cells are within a memory device. 
     
     
         18 . The storage device using semiconductor memory of  claim 17 , wherein the volatile memory device is a DRAM. 
     
     
         19 . The storage device using semiconductor memory of  claim 18 , wherein the memory system comprises a plurality of channels , a plurality of buffer circuits and an error checking and correcting ECC circuit, each of the channels coupled to one of a plurality of nonvolatile memory device, one of a plurality of buffer circuits, and the ECC circuit. 
     
     
         20 . The storage device using semiconductor memory of  claim 15 , wherein the first interface is one of Universal Serial Bus (USB) interfaces, Advanced Technology Attachment (ATA) interfaces, Serial ATA (SATA) interfaces, and Small Computer System Interface (SCSI) interfaces.