Stacked nanowire device with variable number of nanowire channels

Abstract

A method of forming a semiconductor structure including forming a stack of layers on a top surface of a substrate, the stack of layers including alternating layers of a semiconductor material and a sacrificial material, where a bottommost layer of the stack of layers is a top semiconductor layer of the substrate, patterning a plurality of material stacks from the stack of layers, each material stack including an alternating stack of a plurality of nanowire channels and a plurality of sacrificial spacers, the plurality of nanowire channels including the semiconductor material, and the plurality of sacrificial spacers including the sacrificial material, and removing at least one of the plurality of nanowire channels from at least one of the plurality of material stacks without removing one or more of the plurality of nanowire channels from an adjacent material stack.

1 .- 14 . (canceled) 
     
     
         15 . A structure comprising:
 a plurality of vertically stacked and vertically spaced apart nanowire channels located above a substrate, each nanowire channel having two end segments in which one of the end segments is connected to a source region and the other end segment is connected to a drain region, the plurality of vertically stacked and vertically spaced apart nanowire channels are organized in adjacent stacks, and at least one stack of the structure includes a different number of nanowire channels than an adjacent stack;   a gate electrode over a central portion of the plurality of vertically stacked and vertically spaced apart nanowire channels, the source region and the drain region is self-aligned with the gate region; and   a spacer located between each vertically stacked and vertically spaced apart nanowire channel, the spacer also separating the gate electrode from both the source region and the drain region.   
     
     
         16 . The structure of  claim 15 , wherein each of the nanowire channels has a pitch of less than 200 nm and a width of less than 40 nm. 
     
     
         17 . The structure of  claim 15 , wherein each of the nanowire channels comprises a Si-containing semiconductor material. 
     
     
         18 . The structure of  claim 15 , wherein each of the nanowire channels has a height variation of less than or equal to 5%. 
     
     
         19 . The structure of  claim 15 , wherein each vertically stacked and vertically spaced apart nanowire channel is separated by a distance of less than 200 nm. 
     
     
         20 . The structure of  claim 15 , further comprising:
 a dielectric layer located above the source region and the drain region, and surrounding the gate electrode, the dielectric layer having an upper surface that is substantially flush with an upper surface of the gate electrode.   
     
     
         21 . The structure of  claim 15 , further comprising a shallow trench isolation region located at a footprint of each of the vertically stacked and vertically spaced apart nanowire channels. 
     
     
         22 . The structure of  claim 15 , wherein the substrate comprises a least one semiconductor material. 
     
     
         23 . The structure of  claim 15 , wherein each of the nanowire channels comprises a same semiconductor material as said substrate. 
     
     
         24 . The structure of  claim 15 , wherein each of the nanowire channels is single crystalline and has a same crystalline dimension as the substrate. 
     
     
         25 . The structure of  claim 15 , wherein a middle portion of each of the nanowire channels is suspended. 
     
     
         26 . The structure of  claim 25 , wherein the spacer is present on each end portion of each of the nanowire channels. 
     
     
         27 . The structure of  claim 15 , wherein outermost sidewall surfaces of each nanowire channel of each vertically stacked and vertically spaced apart nanowire channels are vertically aligned with each other. 
     
     
         28 . The structure of  claim 15 , wherein a topmost surface of the gate electrode is located above a topmost nanowire channel of each vertically stacked and vertically spaced apart nanowire channels.