Graphene growth on a carbon-containing semiconductor layer

Abstract

A semiconductor-carbon alloy layer is formed on the surface of a semiconductor substrate, which may be a commercially available semiconductor substrate such as a silicon substrate. The semiconductor-carbon alloy layer is converted into at least one graphene layer during a high temperature anneal, during which the semiconductor material on the surface of the semiconductor-carbon alloy layer is evaporated selective to the carbon atoms. As the semiconductor atoms are selectively removed and the carbon concentration on the surface of the semiconductor-carbon alloy layer increases, the remaining carbon atoms in the top layers of the semiconductor-carbon alloy layer coalesce to form a graphene layer having at least one graphene monolayer. Thus, a graphene layer may be provided on a commercially available semiconductor substrate having a diameter of 200 mm or 300 mm.

1 . A semiconductor structure comprising:
 a semiconductor substrate comprising a single crystalline silicon-containing semiconductor material;   a semiconductor carbide layer located on said semiconductor substrate and having a thickness less than 10 nm; and   a graphene layer consisting of a number of graphene monolayers and abutting said semiconductor carbide layer, wherein said number is equal to or greater than 1 and equal to or less than 4, and wherein said graphene layer has a (0001) crystalline orientation along a surface normal of a top surface of said semiconductor substrate.   
     
     
         2 . The semiconductor structure of  claim 1 , wherein said semiconductor carbide layer is one of a silicon carbide layer, a silicon-germanium carbide layer, and a germanium carbide layer. 
     
     
         3 . The semiconductor structure of  claim 2 , wherein said semiconductor carbide layer is located directly on said single crystalline silicon-containing semiconductor material, and said semiconductor carbide layer is single crystalline. 
     
     
         4 . The semiconductor structure of  claim 1 , further comprising a dielectric material portion located directly on a top surface of, or embedded within, said semiconductor substrate, wherein said semiconductor carbide layer is located directly on said dielectric material portion. 
     
     
         5 . The semiconductor structure of  claim 4 , wherein said semiconductor carbide layer is one of a silicon carbide layer, a silicon-germanium carbide layer, and a germanium carbide layer. 
     
     
         6 . The semiconductor structure of  claim 5 , wherein said semiconductor carbide layer is single crystalline over a top surface of said dielectric material portion. 
     
     
         7 . The semiconductor structure of  claim 1 , wherein said semiconductor carbide layer has a single crystalline semiconductor carbide structure that is epitaxially aligned to a single crystalline structure of said single crystalline silicon-containing semiconductor material. 
     
     
         8 . The semiconductor structure of  claim 7 , further comprising a dielectric material portion located directly on a top surface of, or embedded within, said semiconductor substrate, wherein said semiconductor carbide layer is located directly on said dielectric material portion. 
     
     
         9 . The semiconductor structure of  claim 8 , wherein epitaxial alignment of a portion of said semiconductor carbide layer in direct contact with said single crystalline structure of said single crystalline silicon-containing semiconductor material extends over an entirety of a portion of said semiconductor carbide layer that overlies said dielectric material portion. 
     
     
         10 . The semiconductor structure of  claim 7 , wherein said dielectric material portion is one of:
 an overlying dielectric material portion located over a top surface of said semiconductor substrate;   an overlying dielectric material portion located over a portion of a top surface of said semiconductor substrate and between portions of said single crystalline silicon-containing semiconductor material that contact said semiconductor carbide layer; and   
       an embedded dielectric material portion located underneath said semiconductor carbide layer. 
     
     
         11 .- 20 . (canceled)