METHODS FOR CONSTRUCTING THREE DIMENSIONAL (3D) INTEGRATED CIRCUITS (ICs) (3DICs) AND RELATED SYSTEMS

Abstract

Methods for constructing three dimensional integrated circuits and related systems are disclosed. In one aspect, a first tier is constructed by creating active elements such as transistors on a holding substrate. An interconnection metal layer is created above the active elements. Metal bonding pads are created within the interconnection metal layer. A second tier is also created, either concurrently or sequentially. The second tier is created in much the same manner as the first tier and is then placed on the first tier, such that the respective metal bonding pads align and are bonded one tier to the other. The holding substrate of the second tier is then released. A back side of the second tier is then thinned, such that the back surfaces of the active elements (for example, a back of a gate in a transistor) are exposed. Additional tiers may be added if desired essentially repeating this process.

What is claimed is: 
     
         1 . A method of forming a three dimensional (3D) integrated circuit (IC) (3DIC) comprising:
 forming a first tier by:
 providing a first holding substrate; 
 forming a first transistor above the first holding substrate; and 
 forming a first interconnection metal layer above the first transistor including a first metal bonding pad; 
   forming a second tier by:
 providing a second holding substrate; 
 forming a second transistor above the second holding substrate; and 
 forming a second interconnection metal layer above the second transistor including a second metal bonding pad; 
   bonding the first metal bonding pad to the second metal bonding pad; and   releasing the second holding substrate and exposing a second back surface of a second gate of the second transistor.   
     
     
         2 . The method of  claim 1 , wherein either the first holding substrate comprises silicon, the second holding substrate comprises silicon, or both the first and the second holding substrates comprise silicon. 
     
     
         3 . The method of  claim 1 , wherein either the first holding substrate comprises glass, the second holding substrate comprises glass, or both the first and the second holding substrates comprise glass. 
     
     
         4 . The method of  claim 1 , further comprising aligning the first metal bonding pad with the second metal bonding pad before bonding. 
     
     
         5 . The method of  claim 1 , wherein releasing the second holding substrate comprises using a process selected from the group consisting of: chemical mechanical polishing (CMP), etching, ion cutting, and a combination of one or more processes within the group. 
     
     
         6 . The method of  claim 1 , further comprising adding a back gate to the second transistor. 
     
     
         7 . The method of  claim 1 , further comprising adding a third tier above the second tier. 
     
     
         8 . The method of  claim 7 , wherein adding the third tier comprises:
 forming the third tier by:
 providing a third holding substrate; 
 forming a third transistor above the third holding substrate; and 
 forming a third interconnection metal layer above the third transistor including a third metal bonding pad; 
   adding a second back metal above the second back surface including a second upper metal bonding pad; and   bonding the second upper metal bonding pad to the third metal bonding pad.   
     
     
         9 . The method of  claim 8 , further comprising providing a via between the second back metal and the second interconnection metal layer. 
     
     
         10 . The method of  claim 1 , wherein forming the first tier further comprises:
 bonding a first supporting substrate to the first tier above the first transistor; and   releasing the first holding substrate and exposing a first back surface of a first gate of the first transistor; and   wherein adding the first interconnection metal layer above the first transistor comprises adding the first interconnection metal layer above the first back surface of the first gate.   
     
     
         11 . The method of  claim 1 , wherein releasing the second holding substrate comprises detecting a material change between a holding type of material associated with the second holding substrate and a transistor type of material associated with the second transistor. 
     
     
         12 . A method of forming a three dimensional (3D) integrated circuit (IC) (3DIC) comprising:
 forming a first tier by:
 providing a first holding substrate; 
 forming a first transistor above the first holding substrate; 
 forming a first metal layer above the first transistor; 
 bonding a first supporting substrate to the first tier above the first metal layer; 
 releasing the first holding substrate and exposing a first back surface of a first gate of the first transistor; and 
 adding a first interconnection metal layer above the first back surface of the first gate including a first metal bonding pad; 
   forming a second tier by:
 providing a second holding substrate; 
 forming a second transistor above the second holding substrate; and 
 forming a second interconnection metal layer above the second transistor including a second metal bonding pad; 
   bonding the first metal bonding pad to the second metal bonding pad; and   releasing the second holding substrate and exposing a second back surface of a second gate of the second transistor.   
     
     
         13 . The method of  claim 12 , further comprising adding a first back gate proximate the first back surface. 
     
     
         14 . The method of  claim 12 , further comprising adding a second back gate proximate the second back surface. 
     
     
         15 . The method of  claim 12 , further comprising adding a third tier above the second tier. 
     
     
         16 . The method of  claim 12 , further comprising adding a via between the first metal layer and the first interconnection metal layer. 
     
     
         17 . The method of  claim 12 , wherein releasing the first holding substrate comprises using a process selected from the group consisting of: chemical mechanical polishing (CMP), etching, ion cutting, and a combination of one or more processes within the group. 
     
     
         18 . The method of  claim 12 , further comprising detecting a transition between material types when releasing the first holding substrate.